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comparison m68k.cpu @ 2591:563d05355a12

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Cut down on code bloat in 68K core a little
author Michael Pavone <pavone@retrodev.com>
date Sun, 09 Feb 2025 14:15:22 -0800
parents e602dbf776d8
children b0a7b1f708cc
comparison
equal deleted inserted replaced
2590:e602dbf776d8 2591:563d05355a12
2775 #TODO: trap if not in supervisor mode 2775 #TODO: trap if not in supervisor mode
2776 aregs.R = other_sp 2776 aregs.R = other_sp
2777 m68k_prefetch 2777 m68k_prefetch
2778 2778
2779 0111RRR0IIIIIIII moveq 2779 0111RRR0IIIIIIII moveq
2780 nospecialize I
2780 local tmp 32 2781 local tmp 32
2781 sext 16 I tmp 2782 sext 16 I tmp
2782 sext 32 tmp dregs.R 2783 sext 32 tmp dregs.R
2783 cmp 0 dregs.R 2784 cmp 0 dregs.R
2784 update_flags NZV0C0 2785 update_flags NZV0C0
2801 cycles 2 2802 cycles 2
2802 m68k_prefetch 2803 m68k_prefetch
2803 2804
2804 2805
2805 01100001DDDDDDDD bsr 2806 01100001DDDDDDDD bsr
2807 nospecialize D
2806 #mid-instruction timing isn't quite right 2808 #mid-instruction timing isn't quite right
2807 #becuase I'm only emulating a 1-word prefetch buffer instead of 2 2809 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
2808 local offset 32 2810 local offset 32
2809 sext 16 D offset 2811 sext 16 D offset
2810 sext 32 offset offset 2812 sext 32 offset offset
2924 cycles 4 2926 cycles 4
2925 end 2927 end
2926 m68k_prefetch 2928 m68k_prefetch
2927 2929
2928 0110CCCCDDDDDDDD bcc 2930 0110CCCCDDDDDDDD bcc
2931 nospecialize D
2929 #mid-instruction timing isn't quite right 2932 #mid-instruction timing isn't quite right
2930 #becuase I'm only emulating a 1-word prefetch buffer instead of 2 2933 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
2931 local offset 32 2934 local offset 32
2932 m68k_check_cond C 2935 m68k_check_cond C
2933 if istrue 2936 if istrue