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comparison z80_to_x86.c @ 1060:56713dac6a69

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Implement INI
author Michael Pavone <pavone@retrodev.com>
date Mon, 01 Aug 2016 09:48:10 -0700
parents ff46d8fc2de8
children 9b5bb50098d2
comparison
equal deleted inserted replaced
1059:8da967779710 1060:56713dac6a69
2334 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B); 2334 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B);
2335 } 2335 }
2336 } 2336 }
2337 z80_save_reg(inst, opts); 2337 z80_save_reg(inst, opts);
2338 break; 2338 break;
2339 /*case Z80_INI: 2339 case Z80_INI:
2340 case Z80_INIR: 2340 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5
2341 //read from IO (C)
2342 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
2343 call(code, opts->read_io);//T states 3
2344
2345 //undocumented N flag behavior
2346 //flag set on bit 7 of value written
2347 bt_ir(code, 7, opts->gen.scratch1, SZ_B);
2348 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
2349 //save value to be written for flag calculation, as the write func does not
2350 //guarantee that it's preserved across the call
2351 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_B);
2352
2353 //write to (HL)
2354 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
2355 call(code, opts->write_8);//T states 4
2356 cycles(&opts->gen, 1);
2357
2358 //increment HL
2359 if (opts->regs[Z80_HL] >= 0) {
2360 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
2361 } else {
2362 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B);
2363 }
2364 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch1, SZ_B);
2365 if (opts->regs[Z80_C] >= 0) {
2366 add_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
2367 } else {
2368 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_C), opts->gen.scratch1, SZ_B);
2369 }
2370 add_ir(code, 1, opts->gen.scratch1, SZ_B);
2371 //undocumented C and H flag behavior
2372 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
2373 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
2374 //decrement B
2375 if (opts->regs[Z80_B] >= 0) {
2376 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
2377 mov_rrdisp(code, opts->regs[Z80_B], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
2378 } else {
2379 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B);
2380 }
2381 //undocumented Z and S flag behavior, set based on decrement of B
2382 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
2383 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
2384 //crazy undocumented P/V flag behavior
2385 and_ir(code, 7, opts->gen.scratch1, SZ_B);
2386 if (opts->regs[Z80_B] >= 0) {
2387 //deal with silly x86-64 restrictions on *H registers
2388 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
2389 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
2390 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W);
2391 } else {
2392 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B);
2393 }
2394 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
2395 break;
2396 /*case Z80_INIR:
2341 case Z80_IND: 2397 case Z80_IND:
2342 case Z80_INDR:*/ 2398 case Z80_INDR:*/
2343 case Z80_OUT: 2399 case Z80_OUT:
2344 if (inst->reg == Z80_A) { 2400 if (inst->reg == Z80_A) {
2345 num_cycles += 3; 2401 num_cycles += 3;