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comparison vdp.c @ 2334:57ebbc1ade30

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Fix regression in mega-color image demos
author Michael Pavone <pavone@retrodev.com>
date Sat, 26 Aug 2023 19:59:44 -0700
parents 6f6f21d0c396
children 83f5529086c5
comparison
equal deleted inserted replaced
2333:866577a220e6 2334:57ebbc1ade30
590 #define VSRAM_READ 4 //0100 590 #define VSRAM_READ 4 //0100
591 #define VSRAM_WRITE 5//0101 591 #define VSRAM_WRITE 5//0101
592 //6 would trigger regsiter write 0110 592 //6 would trigger regsiter write 0110
593 //7 is a mystery //0111 593 //7 is a mystery //0111
594 #define CRAM_READ 8 //1000 594 #define CRAM_READ 8 //1000
595 //9 is also a mystery //1001 595 //writes go nowhere, acts 8-bit wide like VRAM //1001
596 //A would trigger register write 1010 596 //A would trigger register write 1010
597 //B is a mystery 1011 597 //B is a mystery 1011
598 #define VRAM_READ8 0xC //1100 598 #define VRAM_READ8 0xC //1100
599 //D is a mystery 1101 599 //writes go nowhere, acts 16-bit wide like VSRAM/CRAM 1101
600 //E would trigger register write 1110 600 //E would trigger register write 1110
601 //F is a mystery 1111 601 //F is a mystery 1111
602 602
603 //Possible theory on how bits work 603 //Possible theory on how bits work
604 //CD0 = Read/Write flag 604 //CD0 = Read/Write flag
1120 event_log(EVENT_VDP_INTRAM, context->cycles, sizeof(buffer), buffer); 1120 event_log(EVENT_VDP_INTRAM, context->cycles, sizeof(buffer), buffer);
1121 } 1121 }
1122 1122
1123 break; 1123 break;
1124 default: 1124 default:
1125 if (!(context->cd & 4) && !start->partial && (context->regs[REG_MODE_2] & (BIT_128K_VRAM|BIT_MODE_5)) != (BIT_128K_VRAM|BIT_MODE_5)) { 1125 if (!(context->cd & 6) && !start->partial && (context->regs[REG_MODE_2] & (BIT_128K_VRAM|BIT_MODE_5)) != (BIT_128K_VRAM|BIT_MODE_5)) {
1126 start->partial = 1; 1126 start->partial = 1;
1127 return; 1127 return;
1128 } 1128 }
1129 } 1129 }
1130 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); 1130 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1);