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comparison z80_to_x86.c @ 840:5822c6e5642f

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Fix timing of IM instruction
author Michael Pavone <pavone@retrodev.com>
date Thu, 29 Oct 2015 21:42:10 -0700
parents 22c3c52b9871
children 58606d16d35c
comparison
equal deleted inserted replaced
839:4556818b6847 840:5822c6e5642f
545 cycles(&opts->gen, 4); 545 cycles(&opts->gen, 4);
546 zreg_to_native(opts, Z80_BC, opts->gen.scratch1); 546 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
547 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_BC), opts->gen.scratch2, SZ_W); 547 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_BC), opts->gen.scratch2, SZ_W);
548 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_BC), SZ_W); 548 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_BC), SZ_W);
549 native_to_zreg(opts, opts->gen.scratch2, Z80_BC); 549 native_to_zreg(opts, opts->gen.scratch2, Z80_BC);
550 550
551 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); 551 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
552 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_HL), opts->gen.scratch2, SZ_W); 552 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_HL), opts->gen.scratch2, SZ_W);
553 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_HL), SZ_W); 553 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_HL), SZ_W);
554 native_to_zreg(opts, opts->gen.scratch2, Z80_HL); 554 native_to_zreg(opts, opts->gen.scratch2, Z80_HL);
555 555
556 zreg_to_native(opts, Z80_DE, opts->gen.scratch1); 556 zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
557 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_DE), opts->gen.scratch2, SZ_W); 557 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_DE), opts->gen.scratch2, SZ_W);
558 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_DE), SZ_W); 558 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_DE), SZ_W);
559 native_to_zreg(opts, opts->gen.scratch2, Z80_DE); 559 native_to_zreg(opts, opts->gen.scratch2, Z80_DE);
560 break; 560 break;
1008 if (dst_op.mode == MODE_REG_DIRECT) { 1008 if (dst_op.mode == MODE_REG_DIRECT) {
1009 sub_ir(code, 1, dst_op.base, z80_size(inst)); 1009 sub_ir(code, 1, dst_op.base, z80_size(inst));
1010 } else { 1010 } else {
1011 sub_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst)); 1011 sub_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst));
1012 } 1012 }
1013 1013
1014 if (z80_size(inst) == SZ_B) { 1014 if (z80_size(inst) == SZ_B) {
1015 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); 1015 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1016 //TODO: Implement half-carry flag 1016 //TODO: Implement half-carry flag
1017 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); 1017 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
1018 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); 1018 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
1082 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles 1082 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles
1083 add_irdisp(code, 4*opts->gen.clock_divider, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D); 1083 add_irdisp(code, 4*opts->gen.clock_divider, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
1084 call(code, opts->do_sync); 1084 call(code, opts->do_sync);
1085 break; 1085 break;
1086 case Z80_IM: 1086 case Z80_IM:
1087 cycles(&opts->gen, 4); 1087 cycles(&opts->gen, 8);
1088 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B); 1088 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B);
1089 break; 1089 break;
1090 case Z80_RLC: 1090 case Z80_RLC:
1091 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); 1091 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
1092 cycles(&opts->gen, num_cycles); 1092 cycles(&opts->gen, num_cycles);