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comparison cpu_dsl.py @ 1708:5bfed2eedc9d

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Fixed flag calculation for sub instructions in CPU DSL
author Michael Pavone <pavone@retrodev.com>
date Mon, 28 Jan 2019 22:37:46 -0800
parents a16088324f30
children 9c058ea77b7a
comparison
equal deleted inserted replaced
1707:a16088324f30 1708:5bfed2eedc9d
238 if needsCarry: 238 if needsCarry:
239 size *= 2 239 size *= 2
240 decl,name = prog.getTemp(size) 240 decl,name = prog.getTemp(size)
241 dst = prog.carryFlowDst = name 241 dst = prog.carryFlowDst = name
242 prog.lastA = a 242 prog.lastA = a
243 prog.lastB = '(-' + b + ')' if op == '-' else b 243 prog.lastB = b
244 prog.lastWasSub = op == '-' 244 prog.lastBFlow = '(-' + b + ')' if op == '-' else b
245 else: 245 else:
246 dst = params[2] 246 dst = params[2]
247 return decl + '\n\t{dst} = {a} {op} {b};'.format( 247 return decl + '\n\t{dst} = {a} {op} {b};'.format(
248 dst = dst, a = a, b = b, op = op 248 dst = dst, a = a, b = b, op = op
249 ) 249 )
311 resultBit = prog.paramSize(prog.lastDst) - 1 311 resultBit = prog.paramSize(prog.lastDst) - 1
312 elif calc == 'carry': 312 elif calc == 'carry':
313 resultBit = prog.paramSize(prog.lastDst) 313 resultBit = prog.paramSize(prog.lastDst)
314 elif calc == 'half': 314 elif calc == 'half':
315 resultBit = 4 315 resultBit = 4
316 fmt = '({a} ^ {b} ^ ~{res})' if prog.lastWasSub else '({a} ^ {b} ^ {res})' 316 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst)
317 myRes = fmt.format(a = prog.lastA, b = prog.lastB, res = lastDst)
318 elif calc == 'overflow': 317 elif calc == 'overflow':
319 resultBit = prog.paramSize(prog.lastDst) - 1 318 resultBit = prog.paramSize(prog.lastDst) - 1
320 myRes = '((~({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastB, res = lastDst) 319 myRes = '((~({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastBFlow, res = lastDst)
321 else: 320 else:
322 resultBit = int(resultBit) 321 resultBit = int(resultBit)
323 if type(storage) is tuple: 322 if type(storage) is tuple:
324 reg,storageBit = storage 323 reg,storageBit = storage
325 reg = prog.resolveParam(reg, None, {}) 324 reg = prog.resolveParam(reg, None, {})
989 self.currentScope = None 988 self.currentScope = None
990 self.lastOp = None 989 self.lastOp = None
991 self.carryFlowDst = None 990 self.carryFlowDst = None
992 self.lastA = None 991 self.lastA = None
993 self.lastB = None 992 self.lastB = None
994 self.lastWasSub = False 993 self.lastBFlow = None
995 994
996 def __str__(self): 995 def __str__(self):
997 pieces = [] 996 pieces = []
998 for reg in self.regs: 997 for reg in self.regs:
999 pieces.append(str(self.regs[reg])) 998 pieces.append(str(self.regs[reg]))