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comparison ym2612.h @ 1692:5dacaef602a7 segacd

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Merge from default
author Michael Pavone <pavone@retrodev.com>
date Sat, 05 Jan 2019 00:58:08 -0800
parents 804f13c090b4
children 5278b6e44fc1
comparison
equal deleted inserted replaced
1504:95b3a1a8b26c 1692:5dacaef602a7
7 #define YM2612_H_ 7 #define YM2612_H_
8 8
9 #include <stdint.h> 9 #include <stdint.h>
10 #include <stdio.h> 10 #include <stdio.h>
11 #include "serialize.h" 11 #include "serialize.h"
12 #include "render.h"
12 13
13 #define NUM_PART_REGS (0xB7-0x30) 14 #define NUM_PART_REGS (0xB7-0x30)
14 #define NUM_CHANNELS 6 15 #define NUM_CHANNELS 6
15 #define NUM_OPERATORS (4*NUM_CHANNELS) 16 #define NUM_OPERATORS (4*NUM_CHANNELS)
16 17
17 #define YM_OPT_WAVE_LOG 1 18 #define YM_OPT_WAVE_LOG 1
18 19
19 typedef struct { 20 typedef struct {
21 int16_t *mod_src[2];
20 uint32_t phase_counter; 22 uint32_t phase_counter;
21 uint16_t envelope; 23 uint16_t envelope;
22 int16_t output; 24 int16_t output;
23 uint16_t total_level; 25 uint16_t total_level;
24 uint16_t sustain_level; 26 uint16_t sustain_level;
60 #define YM_REG_END 0xB8 62 #define YM_REG_END 0xB8
61 #define YM_PART1_REGS (YM_REG_END-YM_PART1_START) 63 #define YM_PART1_REGS (YM_REG_END-YM_PART1_START)
62 #define YM_PART2_REGS (YM_REG_END-YM_PART2_START) 64 #define YM_PART2_REGS (YM_REG_END-YM_PART2_START)
63 65
64 typedef struct { 66 typedef struct {
65 int16_t *audio_buffer; 67 audio_source *audio;
66 int16_t *back_buffer;
67 uint64_t buffer_fraction;
68 uint64_t buffer_inc;
69 uint32_t clock_inc; 68 uint32_t clock_inc;
70 uint32_t buffer_pos;
71 uint32_t sample_rate;
72 uint32_t sample_limit;
73 uint32_t current_cycle; 69 uint32_t current_cycle;
74 //TODO: Condense the next two fields into one 70 //TODO: Condense the next two fields into one
75 uint32_t write_cycle; 71 uint32_t write_cycle;
76 uint32_t busy_cycles; 72 uint32_t busy_cycles;
77 uint32_t lowpass_alpha; 73 uint32_t lowpass_alpha;
79 ym_channel channels[NUM_CHANNELS]; 75 ym_channel channels[NUM_CHANNELS];
80 uint16_t timer_a; 76 uint16_t timer_a;
81 uint16_t timer_a_load; 77 uint16_t timer_a_load;
82 uint16_t env_counter; 78 uint16_t env_counter;
83 ym_supp ch3_supp[3]; 79 ym_supp ch3_supp[3];
84 int16_t last_left;
85 int16_t last_right;
86 uint8_t timer_b; 80 uint8_t timer_b;
87 uint8_t sub_timer_b; 81 uint8_t sub_timer_b;
88 uint8_t timer_b_load; 82 uint8_t timer_b_load;
89 uint8_t ch3_mode; 83 uint8_t ch3_mode;
90 uint8_t current_op; 84 uint8_t current_op;
129 REG_BLOCK_FN_CH3 = 0xAC, 123 REG_BLOCK_FN_CH3 = 0xAC,
130 REG_ALG_FEEDBACK = 0xB0, 124 REG_ALG_FEEDBACK = 0xB0,
131 REG_LR_AMS_PMS = 0xB4 125 REG_LR_AMS_PMS = 0xB4
132 }; 126 };
133 127
134 void ym_init(ym2612_context * context, uint32_t sample_rate, uint32_t master_clock, uint32_t clock_div, uint32_t sample_limit, uint32_t options, uint32_t lowpass_cutoff); 128 void ym_init(ym2612_context * context, uint32_t master_clock, uint32_t clock_div, uint32_t options);
135 void ym_reset(ym2612_context *context); 129 void ym_reset(ym2612_context *context);
136 void ym_free(ym2612_context *context); 130 void ym_free(ym2612_context *context);
137 void ym_adjust_master_clock(ym2612_context * context, uint32_t master_clock); 131 void ym_adjust_master_clock(ym2612_context * context, uint32_t master_clock);
138 void ym_run(ym2612_context * context, uint32_t to_cycle); 132 void ym_run(ym2612_context * context, uint32_t to_cycle);
139 void ym_address_write_part1(ym2612_context * context, uint8_t address); 133 void ym_address_write_part1(ym2612_context * context, uint8_t address);