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comparison vdp.c @ 452:608815ab4ff2

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Merge
author Mike Pavone <pavone@retrodev.com>
date Sun, 01 Sep 2013 14:27:17 -0700
parents b7c3b2d22858 3758bcdae5de
children b491df8bdbc0
comparison
equal deleted inserted replaced
451:b7c3b2d22858 452:608815ab4ff2
476 } 476 }
477 dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; 477 dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1;
478 context->regs[REG_DMALEN_H] = dma_len >> 8; 478 context->regs[REG_DMALEN_H] = dma_len >> 8;
479 context->regs[REG_DMALEN_L] = dma_len; 479 context->regs[REG_DMALEN_L] = dma_len;
480 if (!dma_len) { 480 if (!dma_len) {
481 printf("DMA end at cycle %d\n", context->cycles);
481 context->flags &= ~FLAG_DMA_RUN; 482 context->flags &= ~FLAG_DMA_RUN;
482 } 483 }
483 } 484 }
484 } else { 485 } else {
485 fifo_entry * start = (context->fifo_end - FIFO_SIZE); 486 fifo_entry * start = (context->fifo_end - FIFO_SIZE);
486 if (context->fifo_cur != start && start->cycle <= context->cycles) { 487 if (context->fifo_cur != start && start->cycle <= context->cycles) {
487 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START)) { 488 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) {
489 printf("DMA fill started at %d\n", context->cycles);
488 context->flags |= FLAG_DMA_RUN; 490 context->flags |= FLAG_DMA_RUN;
489 context->dma_val = start->value; 491 context->dma_val = start->value;
490 context->address = start->address; //undo auto-increment 492 context->address = start->address; //undo auto-increment
491 context->dma_cd = context->cd; 493 context->dma_cd = context->cd;
492 } else { 494 } else {
1456 } 1458 }
1457 } 1459 }
1458 1460
1459 int vdp_control_port_write(vdp_context * context, uint16_t value) 1461 int vdp_control_port_write(vdp_context * context, uint16_t value)
1460 { 1462 {
1461 //printf("control port write: %X\n", value); 1463 printf("control port write: %X at %d\n", value, context->cycles);
1462 if (context->flags & FLAG_DMA_RUN) { 1464 if (context->flags & FLAG_DMA_RUN) {
1463 return -1; 1465 return -1;
1464 } 1466 }
1465 if (context->flags & FLAG_PENDING) { 1467 if (context->flags & FLAG_PENDING) {
1466 context->address = (context->address & 0x3FFF) | (value << 14); 1468 context->address = (context->address & 0x3FFF) | (value << 14);
1467 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); 1469 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C);
1468 context->flags &= ~FLAG_PENDING; 1470 context->flags &= ~FLAG_PENDING;
1469 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); 1471 printf("New Address: %X, New CD: %X\n", context->address, context->cd);
1470 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { 1472 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) {
1471 // 1473 //
1472 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { 1474 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) {
1473 //DMA copy or 68K -> VDP, transfer starts immediately 1475 //DMA copy or 68K -> VDP, transfer starts immediately
1474 context->flags |= FLAG_DMA_RUN; 1476 context->flags |= FLAG_DMA_RUN;
1475 context->dma_cd = context->cd; 1477 context->dma_cd = context->cd;
1478 printf("DMA start at cycle %d\n", context->cycles);
1476 if (!(context->regs[REG_DMASRC_H] & 0x80)) { 1479 if (!(context->regs[REG_DMASRC_H] & 0x80)) {
1477 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); 1480 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]);
1478 return 1; 1481 return 1;
1479 } else { 1482 } else {
1480 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); 1483 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
1481 } 1484 }
1482 } else { 1485 } else {
1483 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); 1486 printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd);
1484 } 1487 }
1485 } 1488 }
1486 } else { 1489 } else {
1487 if ((value & 0xC000) == 0x8000) { 1490 if ((value & 0xC000) == 0x8000) {
1488 //Register write 1491 //Register write
1489 uint8_t reg = (value >> 8) & 0x1F; 1492 uint8_t reg = (value >> 8) & 0x1F;
1490 if (reg < VDP_REGS) { 1493 if (reg < VDP_REGS) {
1491 //printf("register %d set to %X\n", reg, value & 0xFF); 1494 printf("register %d set to %X\n", reg, value & 0xFF);
1492 context->regs[reg] = value; 1495 context->regs[reg] = value;
1493 if (reg == REG_MODE_2) { 1496 if (reg == REG_MODE_2) {
1494 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled"); 1497 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled");
1495 } 1498 }
1496 if (reg == REG_MODE_4) { 1499 if (reg == REG_MODE_4) {
1509 return 0; 1512 return 0;
1510 } 1513 }
1511 1514
1512 int vdp_data_port_write(vdp_context * context, uint16_t value) 1515 int vdp_data_port_write(vdp_context * context, uint16_t value)
1513 { 1516 {
1514 //printf("data port write: %X\n", value); 1517 printf("data port write: %X at %d\n", value, context->cycles);
1515 if (context->flags & FLAG_DMA_RUN) { 1518 if (context->flags & FLAG_DMA_RUN) {
1516 return -1; 1519 return -1;
1517 } 1520 }
1518 if (!(context->cd & 1)) { 1521 if (!(context->cd & 1)) {
1519 //ignore writes when cd is configured for read 1522 //ignore writes when cd is configured for read