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Fix cycle counts for a number of instructions in new 68K core
author Michael Pavone <pavone@retrodev.com>
date Sun, 18 Feb 2024 22:34:51 -0800
parents d1eec03dca09
children 7d7525769ce2
comparison
equal deleted inserted replaced
2449:bb6cc45518e6 2450:6c93869babc1
425 invalid M 7 R 5 425 invalid M 7 R 5
426 invalid M 7 R 6 426 invalid M 7 R 6
427 invalid M 7 R 7 427 invalid M 7 R 7
428 local size 16 428 local size 16
429 local ext_src 32 429 local ext_src 32
430 #TODO: ensure "penalty" cycles are in the right place
430 if Z 431 if Z
431 mov 2 size 432 size = 2
433 switch M
434 case 0
435 #dreg src
436 cycles 4
437 case 1
438 #areg src
439 cycles 4
440 case 7
441 if R = 4
442 #immediate
443 cycles 4
444 else
445 cycles 2
446 end
447 default
448 cycles 2
449 end
432 else 450 else
433 mov 1 size 451 size = 1
452 cycles 4
434 end 453 end
435 m68k_fetch_src_ea M R size 454 m68k_fetch_src_ea M R size
436 switch size 455 switch size
437 case 1 456 case 1
438 sext 32 src ext_src 457 sext 32 src ext_src
457 switch Z 476 switch Z
458 case 2 477 case 2
459 lsl prefetch 16 immed 478 lsl prefetch 16 immed
460 m68k_prefetch 479 m68k_prefetch
461 or prefetch immed immed 480 or prefetch immed immed
481 if M = 0
482 cycles 4
483 end
462 default 484 default
463 mov prefetch immed 485 mov prefetch immed
464 end 486 end
465 #fetch dst EA 487 #fetch dst EA
466 m68k_fetch_dst_ea M R Z 488 m68k_fetch_dst_ea M R Z
502 invalid Z 3 524 invalid Z 3
503 adc dregs.S dregs.D dregs.D Z 525 adc dregs.S dregs.D dregs.D Z
504 update_flags XNVC 526 update_flags XNVC
505 switch Z 527 switch Z
506 case 0 528 case 0
507 local tmp8 8 529 local tmp8 8
508 mov dregs.D tmp8 530 mov dregs.D tmp8
509 if tmp8 531 if tmp8
510 update_flags Z0 532 update_flags Z0
511 end 533 end
512 case 1 534 case 1
513 local tmp16 16 535 local tmp16 16
514 mov dregs.D tmp16 536 mov dregs.D tmp16
515 if tmp16 537 if tmp16
516 update_flags Z0 538 update_flags Z0
517 end 539 end
518 case 2 540 case 2
519 if dregs.D 541 cycles 4
520 update_flags Z0 542 if dregs.D
521 end 543 update_flags Z0
544 end
522 end 545 end
523 m68k_prefetch 546 m68k_prefetch
524 547
525 1101DDD1ZZ001SSS addx_ay_ax 548 1101DDD1ZZ001SSS addx_ay_ax
526 invalid Z 3 549 invalid Z 3
532 sub 2 aregs.S aregs.S 555 sub 2 aregs.S aregs.S
533 default 556 default
534 decsize Z aregs.S aregs.S 557 decsize Z aregs.S aregs.S
535 end 558 end
536 end 559 end
560 #predec penalty on src only
561 cycles 2
537 mov aregs.S scratch1 562 mov aregs.S scratch1
538 switch Z 563 switch Z
539 case 0 564 case 0
540 ocall read_8 565 ocall read_8
541 case 1 566 case 1
631 switch Z 656 switch Z
632 case 2 657 case 2
633 lsl prefetch 16 immed 658 lsl prefetch 16 immed
634 m68k_prefetch 659 m68k_prefetch
635 or prefetch immed immed 660 or prefetch immed immed
661 if M = 0
662 cycles 4
663 end
636 default 664 default
637 mov prefetch immed 665 mov prefetch immed
638 end 666 end
639 #fetch dst EA 667 #fetch dst EA
640 m68k_fetch_dst_ea M R Z 668 m68k_fetch_dst_ea M R Z
658 invalid M 7 R 5 686 invalid M 7 R 5
659 invalid M 7 R 6 687 invalid M 7 R 6
660 invalid M 7 R 7 688 invalid M 7 R 7
661 invalid Z 3 689 invalid Z 3
662 m68k_fetch_dst_ea M R Z 690 m68k_fetch_dst_ea M R Z
663 691
692 if Z = 2
693 if M = 0
694 cycles 4
695 end
696 end
697
664 xor dregs.D dst dst Z 698 xor dregs.D dst dst Z
665 update_flags NZV0C0 699 update_flags NZV0C0
666 m68k_save_dst Z 700 m68k_save_dst Z
667 m68k_prefetch 701 m68k_prefetch
668 702
681 switch Z 715 switch Z
682 case 2 716 case 2
683 lsl prefetch 16 immed 717 lsl prefetch 16 immed
684 m68k_prefetch 718 m68k_prefetch
685 or prefetch immed immed 719 or prefetch immed immed
720 if M = 0
721 cycles 4
722 end
686 default 723 default
687 mov prefetch immed 724 mov prefetch immed
688 end 725 end
689 #fetch dst EA 726 #fetch dst EA
690 m68k_fetch_dst_ea M R Z 727 m68k_fetch_dst_ea M R Z
705 invalid M 7 R 5 742 invalid M 7 R 5
706 invalid M 7 R 6 743 invalid M 7 R 6
707 invalid M 7 R 7 744 invalid M 7 R 7
708 invalid Z 3 745 invalid Z 3
709 m68k_fetch_src_ea M R Z 746 m68k_fetch_src_ea M R Z
710 747
748 if Z = 2
749 switch M
750 case 0
751 #dreg
752 cycles 4
753 case 7
754 if R = 4
755 #immediate
756 cycles 4
757 else
758 cycles 2
759 end
760 default
761 cycles 2
762 end
763 end
764
711 or src dregs.D dregs.D Z 765 or src dregs.D dregs.D Z
712 update_flags NZV0C0 766 update_flags NZV0C0
713 m68k_prefetch 767 m68k_prefetch
714 768
715 1000DDD1ZZMMMRRR or_dn_ea 769 1000DDD1ZZMMMRRR or_dn_ea
744 switch Z 798 switch Z
745 case 2 799 case 2
746 lsl prefetch 16 immed 800 lsl prefetch 16 immed
747 m68k_prefetch 801 m68k_prefetch
748 or prefetch immed immed 802 or prefetch immed immed
803 if M = 0
804 cycles 4
805 end
749 default 806 default
750 mov prefetch immed 807 mov prefetch immed
751 end 808 end
752 #fetch dst EA 809 #fetch dst EA
753 m68k_fetch_dst_ea M R Z 810 m68k_fetch_dst_ea M R Z
796 invalid M 7 R 6 853 invalid M 7 R 6
797 invalid M 7 R 7 854 invalid M 7 R 7
798 local size 16 855 local size 16
799 local ext_src 32 856 local ext_src 32
800 if Z 857 if Z
801 mov 2 size 858 size = 2
859 switch M
860 case 0
861 #dreg src
862 cycles 4
863 case 1
864 #areg src
865 cycles 4
866 case 7
867 if R = 4
868 #immediate
869 cycles 4
870 else
871 cycles 2
872 end
873 default
874 cycles 2
875 end
802 else 876 else
803 mov 1 size 877 size = 1
878 cycles 4
804 end 879 end
805 m68k_fetch_src_ea M R size 880 m68k_fetch_src_ea M R size
806 switch size 881 switch size
807 case 1 882 case 1
808 sext 32 src ext_src 883 sext 32 src ext_src
827 switch Z 902 switch Z
828 case 2 903 case 2
829 lsl prefetch 16 immed 904 lsl prefetch 16 immed
830 m68k_prefetch 905 m68k_prefetch
831 or prefetch immed immed 906 or prefetch immed immed
907 if M = 0
908 cycles 4
909 end
832 default 910 default
833 mov prefetch immed 911 mov prefetch immed
834 end 912 end
835 #fetch dst EA 913 #fetch dst EA
836 m68k_fetch_dst_ea M R Z 914 m68k_fetch_dst_ea M R Z
930 default 1008 default
931 meta shift C 1009 meta shift C
932 end 1010 end
933 lsl dregs.R shift dregs.R Z 1011 lsl dregs.R shift dregs.R Z
934 update_flags XNZV0C 1012 update_flags XNZV0C
935 add shift shift shift 1013 local cyc 32
936 switch Z 1014 cyc = shift + shift
937 case 2 1015 switch Z
938 add 4 shift shift 1016 case 2
939 default 1017 cyc += 4
940 add 2 shift shift 1018 default
941 end 1019 cyc += 2
942 cycles shift 1020 end
1021 cycles cyc
943 #TODO: should this happen before or after the majority of the shift? 1022 #TODO: should this happen before or after the majority of the shift?
944 m68k_prefetch 1023 m68k_prefetch
945 1024
946 1110CCC1ZZ101RRR lsl_dn 1025 1110CCC1ZZ101RRR lsl_dn
947 invalid Z 3 1026 invalid Z 3
1188 invalid M 7 R 5 1267 invalid M 7 R 5
1189 invalid M 7 R 6 1268 invalid M 7 R 6
1190 invalid M 7 R 7 1269 invalid M 7 R 7
1191 invalid Z 3 1270 invalid Z 3
1192 m68k_fetch_dst_ea M R Z 1271 m68k_fetch_dst_ea M R Z
1272 if Z = 2
1273 if M = 0
1274 #register clears have 2 cycle penalty for longword size
1275 cycles 2
1276 end
1277 end
1193 dst:Z = 0 1278 dst:Z = 0
1194 update_flags N0Z1V0C0 1279 update_flags N0Z1V0C0
1195 m68k_save_dst Z 1280 m68k_save_dst Z
1196 m68k_prefetch 1281 m68k_prefetch
1197 1282