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comparison m68k.cpu @ 2501:6cd5a1d76e34

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Implement some more instructions in new 68K core. First light with some old demos
author Michael Pavone <pavone@retrodev.com>
date Wed, 01 May 2024 01:19:30 -0700
parents d44fe974fb85
children ad50530a7c27
comparison
equal deleted inserted replaced
2500:d44fe974fb85 2501:6cd5a1d76e34
1931 invalid M 7 R 5 1931 invalid M 7 R 5
1932 invalid M 7 R 6 1932 invalid M 7 R 6
1933 invalid M 7 R 7 1933 invalid M 7 R 7
1934 1934
1935 a7 -= 4 1935 a7 -= 4
1936 scratch1 = a7 1936 scratch2 = a7
1937 m68k_write32 pc 1937 m68k_write32 pc
1938 1938
1939 m68k_calc_ea M R 2 1939 m68k_calc_ea M R 2
1940 pc = ea 1940 pc = ea
1941 1941
1942 cycles 4 1942 cycles 4
1943 m68k_prefetch 1943 m68k_prefetch
1944 1944
1945 0100111010MMMRRR jmp 1945 0100111011MMMRRR jmp
1946 invalid M 0 1946 invalid M 0
1947 invalid M 1 1947 invalid M 1
1948 invalid M 3 1948 invalid M 3
1949 invalid M 4 1949 invalid M 4
1950 invalid M 7 R 4 1950 invalid M 7 R 4
2127 ea = address 2127 ea = address
2128 end 2128 end
2129 2129
2130 m68k_prefetch 2130 m68k_prefetch
2131 2131
2132 0100111001100RRR move_to_usp
2133 #TODO: trap if not in supervisor mode
2134 other_sp = aregs.R
2135 m68k_prefetch
2136
2137 0100111001101RRR move_from_usp
2138 #TODO: trap if not in supervisor mode
2139 aregs.R = other_sp
2140 m68k_prefetch
2141
2132 0111RRR0IIIIIIII moveq 2142 0111RRR0IIIIIIII moveq
2133 local tmp 32 2143 local tmp 32
2134 sext 16 I tmp 2144 sext 16 I tmp
2135 sext 32 tmp dregs.R 2145 sext 32 tmp dregs.R
2136 cmp 0 dregs.R 2146 cmp 0 dregs.R
2137 update_flags NZV0C0 2147 update_flags NZV0C0
2138 m68k_prefetch 2148 m68k_prefetch
2149
2150 0110000100000000 bsr_w
2151 #mid-instruction timing isn't quite right
2152 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
2153 local offset 32
2154 m68k_prefetch
2155 sext 32 prefetch offset
2156
2157 a7 -= 4
2158 scratch2 = a7
2159 m68k_write32 pc
2160
2161 pc += offset
2162 pc -= 2
2163
2164 cycles 2
2165 m68k_prefetch
2166
2167
2168 01100001DDDDDDDD bsr
2169 #mid-instruction timing isn't quite right
2170 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
2171 local offset 32
2172 sext 16 D offset
2173 sext 32 offset offset
2174
2175 a7 -= 4
2176 scratch2 = a7
2177 m68k_write32 pc
2178
2179 pc += offset
2180
2181 cycles 6
2182 m68k_prefetch
2183
2184 m68k_check_cond
2185 arg cond 16
2186 local invert 8
2187 switch cond
2188 case 0
2189 #true
2190 meta istrue 1
2191 case 1
2192 #false
2193 meta istrue 0
2194 case 2
2195 #high
2196 meta istrue invert
2197 invert = zflag | cflag
2198 invert = !invert
2199 case 3
2200 #low or same
2201 meta istrue invert
2202 invert = zflag | cflag
2203 case 4
2204 #carry clear
2205 meta istrue invert
2206 invert = !cflag
2207 case 5
2208 #carry set
2209 meta istrue cflag
2210 case 6
2211 #not equal
2212 meta istrue invert
2213 invert = !zflag
2214 case 7
2215 #equal
2216 meta istrue zflag
2217 case 8
2218 #overflow clear
2219 meta istrue invert
2220 invert = !vflag
2221 case 9
2222 #overflow set
2223 meta istrue vflag
2224 case 10
2225 #plus
2226 meta istrue invert
2227 invert = !nflag
2228 case 11
2229 #minus
2230 meta istrue nflag
2231 case 12
2232 #greater or equal
2233 meta istrue invert
2234 invert = nflag - vflag
2235 invert = !invert
2236 case 13
2237 #less
2238 meta istrue invert
2239 invert = nflag - vflag
2240 case 14
2241 #greater
2242 meta istrue invert
2243 invert = vflag ^ nflag
2244 invert |= zflag
2245 invert = !invert
2246 case 15
2247 #less or equal
2248 meta istrue invert
2249 invert = vflag ^ nflag
2250 invert |= zflag
2251 end
2252
2253 0110CCCC00000000 bcc_w
2254 #mid-instruction timing isn't quite right
2255 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
2256 local offset 32
2257 m68k_prefetch
2258 m68k_check_cond C
2259 if istrue
2260
2261 sext 32 prefetch offset
2262 pc += offset
2263 pc -= 2
2264 cycles 2
2265 else
2266 cycles 4
2267 end
2268 m68k_prefetch
2269
2270 0110CCCCDDDDDDDD bcc
2271 #mid-instruction timing isn't quite right
2272 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
2273 local offset 32
2274 m68k_check_cond C
2275 if istrue
2276 sext 16 D offset
2277 sext 32 offset offset
2278
2279 pc += offset
2280
2281 cycles 6
2282 else
2283 cycles 4
2284 end
2285 m68k_prefetch
2286
2287 0101CCCC11001RRR dbcc
2288 local offset 32
2289 local tmp 16
2290 m68k_prefetch
2291 m68k_check_cond C
2292 if istrue
2293 cycles 4
2294 else
2295 dregs.R:1 -= 1
2296 tmp = dregs.R
2297 if tmp = 65535
2298 cycles 6
2299 else
2300 sext 32 prefetch offset
2301 pc += offset
2302 pc -= 2
2303 cycles 2
2304 end
2305 end
2306 m68k_prefetch