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comparison m68k_core_x86.c @ 985:751280fb4494

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Fix interrupt latency from STOP instruction status reg changes. Fix modified code patching when non-standard aliases are used. This fixes the demo MDEM's First
author Michael Pavone <pavone@retrodev.com>
date Sun, 24 Apr 2016 21:23:28 -0700
parents 902c53d9c16f
children f680fe746a7d
comparison
equal deleted inserted replaced
984:bd4d698d995b 985:751280fb4494
2119 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) { 2119 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
2120 //leave supervisor mode 2120 //leave supervisor mode
2121 swap_ssp_usp(opts); 2121 swap_ssp_usp(opts);
2122 } 2122 }
2123 code_ptr loop_top = code->cur; 2123 code_ptr loop_top = code->cur;
2124 call(code, opts->do_sync); 2124 call(code, opts->do_sync);
2125 cmp_rr(code, opts->gen.limit, opts->gen.cycles, SZ_D); 2125 cmp_rr(code, opts->gen.limit, opts->gen.cycles, SZ_D);
2126 code_ptr normal_cycle_up = code->cur + 1; 2126 code_ptr normal_cycle_up = code->cur + 1;
2127 jcc(code, CC_A, code->cur + 2); 2127 jcc(code, CC_A, code->cur + 2);
2128 cycles(&opts->gen, BUS); 2128 cycles(&opts->gen, BUS);
2129 code_ptr after_cycle_up = code->cur + 1; 2129 code_ptr after_cycle_up = code->cur + 1;
2130 jmp(code, code->cur + 2); 2130 jmp(code, code->cur + 2);
2131 *normal_cycle_up = code->cur - (normal_cycle_up + 1); 2131 *normal_cycle_up = code->cur - (normal_cycle_up + 1);
2132 mov_rr(code, opts->gen.limit, opts->gen.cycles, SZ_D); 2132 mov_rr(code, opts->gen.limit, opts->gen.cycles, SZ_D);
2133 *after_cycle_up = code->cur - (after_cycle_up+1); 2133 *after_cycle_up = code->cur - (after_cycle_up+1);
2134 cmp_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, int_cycle), opts->gen.cycles, SZ_D); 2134 cmp_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, int_cycle), opts->gen.cycles, SZ_D);
2135 jcc(code, CC_C, loop_top); 2135 jcc(code, CC_C, loop_top);
2136 //set int pending flag so interrupt fires immediately after stop is done
2137 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(m68k_context, int_pending), SZ_B);
2136 } 2138 }
2137 2139
2138 void translate_m68k_trapv(m68k_options *opts, m68kinst *inst) 2140 void translate_m68k_trapv(m68k_options *opts, m68kinst *inst)
2139 { 2141 {
2140 code_info *code = &opts->gen.code; 2142 code_info *code = &opts->gen.code;
2183 } 2185 }
2184 } 2186 }
2185 2187
2186 m68k_context * m68k_handle_code_write(uint32_t address, m68k_context * context) 2188 m68k_context * m68k_handle_code_write(uint32_t address, m68k_context * context)
2187 { 2189 {
2188 uint32_t inst_start = get_instruction_start(context->native_code_map, address | 0xFF0000); 2190 m68k_options * options = context->options;
2191 //TODO: Modify gen_mem_fun so that it passes the raw address instead of the masked one, then remove the OR below
2192 uint32_t inst_start = get_instruction_start(options, context->native_code_map, address | 0xE00000);
2189 if (inst_start) { 2193 if (inst_start) {
2190 m68k_options * options = context->options;
2191 code_info *code = &options->gen.code; 2194 code_info *code = &options->gen.code;
2192 code_ptr dst = get_native_address(context->options, inst_start); 2195 code_ptr dst = get_native_address(context->options, inst_start);
2193 code_info orig = {dst, dst + 128, 0}; 2196 code_info orig = {dst, dst + 128, 0};
2194 mov_ir(&orig, inst_start, options->gen.scratch2, SZ_D); 2197 mov_ir(&orig, inst_start, options->gen.scratch2, SZ_D);
2195 2198