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comparison m68k_to_x86.c @ 168:7b099f2b382b

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Minor optimization and a cycle count fix to lea
author Mike Pavone <pavone@retrodev.com>
date Sun, 06 Jan 2013 12:17:10 -0800
parents f6c7fea1ecf7
children c07713463c91
comparison
equal deleted inserted replaced
167:f6c7fea1ecf7 168:7b099f2b382b
1364 } 1364 }
1365 break; 1365 break;
1366 case MODE_AREG_DISPLACE: 1366 case MODE_AREG_DISPLACE:
1367 dst = cycles(dst, 8); 1367 dst = cycles(dst, 8);
1368 if (dst_reg >= 0) { 1368 if (dst_reg >= 0) {
1369 if (opts->aregs[inst->src.params.regs.pri] >= 0) { 1369 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) {
1370 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D); 1370 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
1371 } else { 1371 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
1372 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D); 1372 } else {
1373 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D);
1374 }
1373 } 1375 }
1374 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D); 1376 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D);
1375 } else { 1377 } else {
1376 if (opts->aregs[inst->src.params.regs.pri] >= 0) { 1378 if (inst->src.params.regs.pri != inst->dst.params.regs.pri) {
1377 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D); 1379 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
1378 } else { 1380 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D);
1379 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); 1381 } else {
1380 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); 1382 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
1383 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
1384 }
1381 } 1385 }
1382 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->dst)), SZ_D); 1386 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
1383 } 1387 }
1384 break; 1388 break;
1385 case MODE_AREG_INDEX_DISP8: 1389 case MODE_AREG_INDEX_DISP8:
1386 dst = cycles(dst, 6);//TODO: Check to make sure this is correct 1390 dst = cycles(dst, 12);
1387 if (opts->aregs[inst->src.params.regs.pri] >= 0) { 1391 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
1388 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D); 1392 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D);
1389 } else { 1393 } else {
1390 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D); 1394 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D);
1391 } 1395 }
1436 } else { 1440 } else {
1437 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); 1441 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
1438 } 1442 }
1439 break; 1443 break;
1440 case MODE_PC_INDEX_DISP8: 1444 case MODE_PC_INDEX_DISP8:
1441 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct 1445 dst = cycles(dst, BUS*3);
1442 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); 1446 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
1443 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; 1447 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
1444 if (inst->src.params.regs.sec & 1) { 1448 if (inst->src.params.regs.sec & 1) {
1445 if (inst->src.params.regs.sec & 0x10) { 1449 if (inst->src.params.regs.sec & 0x10) {
1446 if (opts->aregs[sec_reg] >= 0) { 1450 if (opts->aregs[sec_reg] >= 0) {