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comparison m68k.cpu @ 1991:7d4df6b74263

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Somewhat buggy implementations of shift instructions in new 68K core
author Michael Pavone <pavone@retrodev.com>
date Sat, 13 Jun 2020 00:37:22 -0700
parents 9eec86183aae
children d1eec03dca09
comparison
equal deleted inserted replaced
1990:57ae42c3ab45 1991:7d4df6b74263
858 default 858 default
859 sub src dst dst Z 859 sub src dst dst Z
860 update_flags XNZVC 860 update_flags XNZVC
861 end 861 end
862 m68k_save_dst Z 862 m68k_save_dst Z
863 m68k_prefetch
864
865 1110CCC0ZZ001RRR lsri
866 invalid Z 3
867 switch C
868 case 0
869 meta shift 8
870 default
871 meta shift C
872 end
873 lsr dregs.R shift dregs.R Z
874 update_flags XNZV0C
875 add shift shift shift
876 switch Z
877 case 2
878 add 4 shift shift
879 default
880 add 2 shift shift
881 end
882 cycles shift
883 #TODO: should this happen before or after the majority of the shift?
884 m68k_prefetch
885
886 1110CCC0ZZ101RRR lsr_dn
887 invalid Z 3
888 local shift 8
889 and dregs.C 63 shift
890 lsr dregs.R shift dregs.R Z
891 update_flags XNZV0C
892 add shift shift shift
893 switch Z
894 case 2
895 add 4 shift shift
896 default
897 add 2 shift shift
898 end
899 cycles shift
900 #TODO: should this happen before or after the majority of the shift?
901 m68k_prefetch
902
903 1110001011MMMRRR lsr_ea
904 invalid M 0
905 invalid M 1
906 invalid M 7 R 2
907 invalid M 7 R 3
908 invalid M 7 R 4
909 invalid M 7 R 5
910 invalid M 7 R 6
911 invalid M 7 R 7
912
913 m68k_fetch_dst_ea M R 0
914 lsr dst 1 dst
915 update_flags XNZV0C
916 m68k_save_dst 0
917 m68k_prefetch
918
919 1110CCC1ZZ001RRR lsli
920 invalid Z 3
921 switch C
922 case 0
923 meta shift 8
924 default
925 meta shift C
926 end
927 lsl dregs.R shift dregs.R Z
928 update_flags XNZV0C
929 add shift shift shift
930 switch Z
931 case 2
932 add 4 shift shift
933 default
934 add 2 shift shift
935 end
936 cycles shift
937 #TODO: should this happen before or after the majority of the shift?
938 m68k_prefetch
939
940 1110CCC1ZZ101RRR lsl_dn
941 invalid Z 3
942 local shift 8
943 and dregs.C 63 shift
944 lsl dregs.R shift dregs.R Z
945 update_flags XNZV0C
946 add shift shift shift
947 switch Z
948 case 2
949 add 4 shift shift
950 default
951 add 2 shift shift
952 end
953 cycles shift
954 #TODO: should this happen before or after the majority of the shift?
955 m68k_prefetch
956
957 1110001111MMMRRR lsl_ea
958 invalid M 0
959 invalid M 1
960 invalid M 7 R 2
961 invalid M 7 R 3
962 invalid M 7 R 4
963 invalid M 7 R 5
964 invalid M 7 R 6
965 invalid M 7 R 7
966
967 m68k_fetch_dst_ea M R 0
968 lsl dst 1 dst
969 update_flags XNZV0C
970 m68k_save_dst 0
863 m68k_prefetch 971 m68k_prefetch
864 972
865 00ZZRRRMMMEEESSS move 973 00ZZRRRMMMEEESSS move
866 invalid Z 0 974 invalid Z 0
867 invalid M 1 975 invalid M 1