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comparison vdp.c @ 697:7f96bd1cb1be

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Sync fixes and logging to fix more sync issues
author Michael Pavone <pavone@retrodev.com>
date Mon, 11 May 2015 00:28:47 -0700
parents 4996369f1463
children d8a1fdec68fc
comparison
equal deleted inserted replaced
696:0b2242bbc84a 697:7f96bd1cb1be
22 22
23 #define MCLKS_SLOT_H40 16 23 #define MCLKS_SLOT_H40 16
24 #define MCLKS_SLOT_H32 20 24 #define MCLKS_SLOT_H32 20
25 #define VINT_SLOT_H40 4 //21 slots before HSYNC, 16 during, 10 after 25 #define VINT_SLOT_H40 4 //21 slots before HSYNC, 16 during, 10 after
26 #define VINT_SLOT_H32 23 //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number 26 #define VINT_SLOT_H32 23 //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number
27 #define HSYNC_SLOT_H40 240 27 #define HSYNC_SLOT_H40 234
28 #define HSYNC_END_H40 (240+17) 28 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17)
29 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) 29 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32)
30 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results 30 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results
31 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results 31 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results
32 #define HBLANK_START_H32 233 //should be 147 according to Nemesis which is very different from my test ROM result 32 #define HBLANK_START_H32 233 //should be 147 according to Nemesis which is very different from my test ROM result
33 #define HBLANK_END_H32 0 //should be 5 according to Nemesis, but 0 seems to fit better with my test ROM results 33 #define HBLANK_END_H32 0 //should be 5 according to Nemesis, but 0 seems to fit better with my test ROM results
1418 } 1418 }
1419 } 1419 }
1420 } 1420 }
1421 } 1421 }
1422 1422
1423 uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 19, 20, 20, 20, 19, 20, 20, 20, 19, 20, 20, 20, 19}; 1423 uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19};
1424 1424
1425 void vdp_run_context(vdp_context * context, uint32_t target_cycles) 1425 void vdp_run_context(vdp_context * context, uint32_t target_cycles)
1426 { 1426 {
1427 while(context->cycles < target_cycles) 1427 while(context->cycles < target_cycles)
1428 { 1428 {
1429 context->flags &= ~FLAG_UNUSED_SLOT; 1429 context->flags &= ~FLAG_UNUSED_SLOT;
1430 uint32_t line = context->vcounter; 1430 uint32_t line = context->vcounter;
1431 uint32_t slot = context->hslot;
1432
1433 if (!line && !slot) {
1434 //TODO: Figure out when this actually happens
1435 latch_mode(context);
1436 }
1431 uint32_t inactive_start = context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START; 1437 uint32_t inactive_start = context->latched_mode & BIT_PAL ? PAL_INACTIVE_START : NTSC_INACTIVE_START;
1432 uint32_t slot = context->hslot;
1433 //TODO: Figure out when this actually happens
1434 if (!line && !slot) {
1435 latch_mode(context);
1436 }
1437 1438
1438 uint8_t is_h40 = context->regs[REG_MODE_4] & BIT_H40; 1439 uint8_t is_h40 = context->regs[REG_MODE_4] & BIT_H40;
1439 if (is_h40) { 1440 if (is_h40) {
1440 if (slot == 167) { 1441 if (slot == 167) {
1441 context->cur_slot = MAX_DRAWS-1; 1442 context->cur_slot = MAX_DRAWS-1;
1453 context->slot_counter = MAX_SPRITES_LINE_H32; 1454 context->slot_counter = MAX_SPRITES_LINE_H32;
1454 } 1455 }
1455 } 1456 }
1456 if (is_h40 && slot == LINE_CHANGE_H40 || !is_h40 && slot == LINE_CHANGE_H32) { 1457 if (is_h40 && slot == LINE_CHANGE_H40 || !is_h40 && slot == LINE_CHANGE_H32) {
1457 if (line >= inactive_start) { 1458 if (line >= inactive_start) {
1459 if (line == (inactive_start + 8)) {
1460 context->frame++;
1461 }
1458 context->hint_counter = context->regs[REG_HINT]; 1462 context->hint_counter = context->regs[REG_HINT];
1459 } else if (context->hint_counter) { 1463 } else if (context->hint_counter) {
1460 context->hint_counter--; 1464 context->hint_counter--;
1461 } else { 1465 } else {
1462 context->flags2 |= FLAG2_HINT_PENDING; 1466 context->flags2 |= FLAG2_HINT_PENDING;
1822 1826
1823 uint32_t vdp_cycles_next_line(vdp_context * context) 1827 uint32_t vdp_cycles_next_line(vdp_context * context)
1824 { 1828 {
1825 if (context->regs[REG_MODE_4] & BIT_H40) { 1829 if (context->regs[REG_MODE_4] & BIT_H40) {
1826 if (context->hslot < LINE_CHANGE_H40) { 1830 if (context->hslot < LINE_CHANGE_H40) {
1827 return (HBLANK_START_H40 - context->hslot) * MCLKS_SLOT_H40; 1831 return (LINE_CHANGE_H40 - context->hslot) * MCLKS_SLOT_H40;
1828 } else if (context->hslot < 183) { 1832 } else if (context->hslot < 183) {
1829 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H40) * MCLKS_SLOT_H40; 1833 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H40) * MCLKS_SLOT_H40;
1830 } else if (context->hslot < HSYNC_END_H40){ 1834 } else if (context->hslot < HSYNC_END_H40){
1831 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0; 1835 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0;
1832 uint32_t hsync = 0; 1836 uint32_t hsync = 0;
1914 uint32_t vdp_cycles_to_frame_end(vdp_context * context) 1918 uint32_t vdp_cycles_to_frame_end(vdp_context * context)
1915 { 1919 {
1916 return context->cycles + vdp_cycles_to_line(context, vdp_frame_end_line(context)); 1920 return context->cycles + vdp_cycles_to_line(context, vdp_frame_end_line(context));
1917 } 1921 }
1918 1922
1919 uint8_t vdp_is_frame_over(vdp_context * context)
1920 {
1921 uint32_t frame_end = vdp_frame_end_line(context);
1922 return context->vcounter >= frame_end && context->vcounter < (frame_end + 8);
1923 }
1924
1925 uint32_t vdp_next_hint(vdp_context * context) 1923 uint32_t vdp_next_hint(vdp_context * context)
1926 { 1924 {
1927 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { 1925 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) {
1928 return 0xFFFFFFFF; 1926 return 0xFFFFFFFF;
1929 } 1927 }