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comparison m68k_core_x86.c @ 1284:82838d4c84d9

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Minor fix to timing of "early" overflow case in divs when the dividend is negative
author Michael Pavone <pavone@retrodev.com>
date Fri, 17 Mar 2017 08:05:55 -0700
parents c5821f9de325
children 71b1a080b30c
comparison
equal deleted inserted replaced
1283:188a60def81f 1284:82838d4c84d9
1734 } 1734 }
1735 if (divisor_shift <= dividend) { 1735 if (divisor_shift <= dividend) {
1736 context->flags[FLAG_V] = 1; 1736 context->flags[FLAG_V] = 1;
1737 context->flags[FLAG_N] = 1; 1737 context->flags[FLAG_N] = 1;
1738 context->flags[FLAG_Z] = 0; 1738 context->flags[FLAG_Z] = 0;
1739 //TODO: FIXME - this cycle count probably changes based on whether the dividend is negative 1739 cycles += 2;
1740 context->current_cycle += 16 * context->options->gen.clock_divider; 1740 context->current_cycle += cycles * context->options->gen.clock_divider;
1741 return orig_dividend; 1741 return orig_dividend;
1742 } 1742 }
1743 uint16_t quotient = 0; 1743 uint16_t quotient = 0;
1744 uint16_t bit = 0; 1744 uint16_t bit = 0;
1745 for (int i = 0; i < 15; i++) 1745 for (int i = 0; i < 15; i++)