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comparison z80_to_x86.c @ 303:8290d3086ff0

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BIT was setting the zero flag to the opposite of what it should have. This is now fixed.
author Mike Pavone <pavone@retrodev.com>
date Wed, 08 May 2013 23:17:54 -0700
parents 3b831fe32c15
children 8dcc9d14413c
comparison
equal deleted inserted replaced
302:3b831fe32c15 303:8290d3086ff0
1157 if (inst->addr_mode != Z80_REG) { 1157 if (inst->addr_mode != Z80_REG) {
1158 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 1158 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
1159 dst = zcycles(dst, 1); 1159 dst = zcycles(dst, 1);
1160 } 1160 }
1161 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B); 1161 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B);
1162 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); 1162 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_Z));
1163 break; 1163 break;
1164 case Z80_SET: 1164 case Z80_SET:
1165 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; 1165 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
1166 dst = zcycles(dst, cycles); 1166 dst = zcycles(dst, cycles);
1167 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY); 1167 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY);