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comparison z80_to_x86.c @ 1767:8a29c250f352

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More instruction timing fixes in old Z80 core
author Michael Pavone <pavone@retrodev.com>
date Mon, 25 Feb 2019 21:22:14 -0800
parents 873a1330c3a9
children 37afb9cf58be
comparison
equal deleted inserted replaced
1766:1dc718581aac 1767:8a29c250f352
353 if (size != SZ_B) { 353 if (size != SZ_B) {
354 num_cycles += 2; 354 num_cycles += 2;
355 } 355 }
356 if (inst->reg == Z80_I || inst->ea_reg == Z80_I || inst->reg == Z80_R || inst->ea_reg == Z80_R) { 356 if (inst->reg == Z80_I || inst->ea_reg == Z80_I || inst->reg == Z80_R || inst->ea_reg == Z80_R) {
357 num_cycles += 1; 357 num_cycles += 1;
358 } else if (inst->reg == Z80_USE_IMMED) {
359 num_cycles += 3;
358 } 360 }
359 break; 361 break;
360 case Z80_IMMED: 362 case Z80_IMMED:
361 num_cycles += size == SZ_B ? 3 : 6; 363 num_cycles += size == SZ_B ? 3 : 6;
362 break; 364 break;
365 break; 367 break;
366 case Z80_IX_DISPLACE: 368 case Z80_IX_DISPLACE:
367 case Z80_IY_DISPLACE: 369 case Z80_IY_DISPLACE:
368 num_cycles += 8; //3 for displacement, 5 for address addition 370 num_cycles += 8; //3 for displacement, 5 for address addition
369 break; 371 break;
370 }
371 if (inst->reg == Z80_USE_IMMED) {
372 num_cycles += 3;
373 } 372 }
374 cycles(&opts->gen, num_cycles); 373 cycles(&opts->gen, num_cycles);
375 if (inst->addr_mode & Z80_DIR) { 374 if (inst->addr_mode & Z80_DIR) {
376 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY); 375 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY);
377 translate_z80_reg(inst, &src_op, opts); 376 translate_z80_reg(inst, &src_op, opts);
943 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { 942 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
944 num_cycles += 8; 943 num_cycles += 8;
945 } else if(inst->addr_mode == Z80_IMMED) { 944 } else if(inst->addr_mode == Z80_IMMED) {
946 num_cycles += 3; 945 num_cycles += 3;
947 } else if(z80_size(inst) == SZ_W) { 946 } else if(z80_size(inst) == SZ_W) {
948 num_cycles += 4; 947 num_cycles += 7;
949 } 948 }
950 cycles(&opts->gen, num_cycles); 949 cycles(&opts->gen, num_cycles);
951 translate_z80_reg(inst, &dst_op, opts); 950 translate_z80_reg(inst, &dst_op, opts);
952 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); 951 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
953 if (dst_op.mode == MODE_REG_DIRECT) { 952 if (dst_op.mode == MODE_REG_DIRECT) {
1074 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { 1073 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1075 num_cycles += 8; 1074 num_cycles += 8;
1076 } else if(inst->addr_mode == Z80_IMMED) { 1075 } else if(inst->addr_mode == Z80_IMMED) {
1077 num_cycles += 3; 1076 num_cycles += 3;
1078 } else if(z80_size(inst) == SZ_W) { 1077 } else if(z80_size(inst) == SZ_W) {
1079 num_cycles += 4; 1078 num_cycles += 7;
1080 } 1079 }
1081 cycles(&opts->gen, num_cycles); 1080 cycles(&opts->gen, num_cycles);
1082 translate_z80_reg(inst, &dst_op, opts); 1081 translate_z80_reg(inst, &dst_op, opts);
1083 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); 1082 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
1084 if (dst_op.mode == MODE_REG_DIRECT) { 1083 if (dst_op.mode == MODE_REG_DIRECT) {
1262 break; 1261 break;
1263 case Z80_INC: 1262 case Z80_INC:
1264 case Z80_DEC: 1263 case Z80_DEC:
1265 if(z80_size(inst) == SZ_W) { 1264 if(z80_size(inst) == SZ_W) {
1266 num_cycles += 2; 1265 num_cycles += 2;
1266 } else if (inst->addr_mode == Z80_REG_INDIRECT) {
1267 num_cycles += 1;
1268 } else if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1269 num_cycles += 9;
1267 } 1270 }
1268 cycles(&opts->gen, num_cycles); 1271 cycles(&opts->gen, num_cycles);
1269 translate_z80_reg(inst, &dst_op, opts); 1272 translate_z80_reg(inst, &dst_op, opts);
1270 if (dst_op.mode == MODE_UNUSED) { 1273 if (dst_op.mode == MODE_UNUSED) {
1271 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); 1274 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
1915 } 1918 }
1916 break; 1919 break;
1917 } 1920 }
1918 case Z80_SET: { 1921 case Z80_SET: {
1919 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { 1922 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1920 num_cycles += 8; 1923 num_cycles += 4;
1921 } 1924 }
1922 cycles(&opts->gen, num_cycles); 1925 cycles(&opts->gen, num_cycles);
1923 uint8_t bit; 1926 uint8_t bit;
1924 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { 1927 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1925 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; 1928 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
1984 } 1987 }
1985 break; 1988 break;
1986 } 1989 }
1987 case Z80_RES: { 1990 case Z80_RES: {
1988 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { 1991 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) {
1989 num_cycles += 8; 1992 num_cycles += 4;
1990 } 1993 }
1991 cycles(&opts->gen, num_cycles); 1994 cycles(&opts->gen, num_cycles);
1992 uint8_t bit; 1995 uint8_t bit;
1993 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { 1996 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1994 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; 1997 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];