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comparison lc8951.c @ 2231:8e6fb2c06024

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Fix CDC transfer regression
author Michael Pavone <pavone@retrodev.com>
date Thu, 08 Sep 2022 18:56:34 -0700
parents 8a30e44e8223
children 5c28534e6e09
comparison
equal deleted inserted replaced
2230:3888c7ed4e36 2231:8e6fb2c06024
141 if (context->ifctrl & BIT_DOUTEN) { 141 if (context->ifctrl & BIT_DOUTEN) {
142 context->regs[IFSTAT] &= ~BIT_DTBSY; 142 context->regs[IFSTAT] &= ~BIT_DTBSY;
143 uint16_t transfer_size = context->regs[DBCL] | (context->regs[DBCH] << 8); 143 uint16_t transfer_size = context->regs[DBCL] | (context->regs[DBCH] << 8);
144 context->transfer_end = context->cycle + transfer_size * context->cycles_per_byte; 144 context->transfer_end = context->cycle + transfer_size * context->cycles_per_byte;
145 context->next_byte_cycle = context->cycle; 145 context->next_byte_cycle = context->cycle;
146 context->triggered = 1;
146 printf("DTTRG: size %u, cycle %u, end %u\n", transfer_size, context->cycle, context->transfer_end); 147 printf("DTTRG: size %u, cycle %u, end %u\n", transfer_size, context->cycle, context->transfer_end);
147 } 148 }
148 break; 149 break;
149 case DTACK: 150 case DTACK:
150 context->regs[IFSTAT] |= BIT_DTEI; 151 context->regs[IFSTAT] |= BIT_DTEI;
276 if (context->cycle != context->transfer_end) { 277 if (context->cycle != context->transfer_end) {
277 printf("Expected transfer end at %u but ended at %u\n", context->transfer_end, context->cycle); 278 printf("Expected transfer end at %u but ended at %u\n", context->transfer_end, context->cycle);
278 } 279 }
279 context->transfer_end = CYCLE_NEVER; 280 context->transfer_end = CYCLE_NEVER;
280 context->next_byte_cycle = CYCLE_NEVER; 281 context->next_byte_cycle = CYCLE_NEVER;
282 context->triggered = 0;
281 } 283 }
282 } 284 }
283 } else { 285 } else {
284 // pause transfer 286 // pause transfer
285 context->next_byte_cycle = CYCLE_NEVER; 287 context->next_byte_cycle = CYCLE_NEVER;
289 } 291 }
290 } 292 }
291 293
292 void lc8951_resume_transfer(lc8951 *context, uint32_t cycle) 294 void lc8951_resume_transfer(lc8951 *context, uint32_t cycle)
293 { 295 {
294 if (context->transfer_end == CYCLE_NEVER && (context->ifctrl & BIT_DOUTEN)) { 296 if (context->triggered && context->transfer_end == CYCLE_NEVER && (context->ifctrl & BIT_DOUTEN)) {
295 uint16_t transfer_size = context->regs[DBCL] | (context->regs[DBCH] << 8); 297 uint16_t transfer_size = context->regs[DBCL] | (context->regs[DBCH] << 8);
296 if (transfer_size != 0xFFFF) { 298 //HACK!!! Work around Sub CPU running longer than we would like and dragging other components with it
297 //HACK!!! Work around Sub CPU running longer than we would like and dragging other components with it 299 uint32_t step_diff = (context->cycle - cycle) / context->clock_step;
298 uint32_t step_diff = (context->cycle - cycle) / context->clock_step; 300 if (step_diff) {
299 if (step_diff) { 301 context->cycle -= step_diff * context->clock_step;
300 context->cycle -= step_diff * context->clock_step; 302 }
301 } 303 context->transfer_end = context->cycle + transfer_size * context->cycles_per_byte;
302 context->transfer_end = context->cycle + transfer_size * context->cycles_per_byte; 304 context->next_byte_cycle = context->cycle;
303 context->next_byte_cycle = context->cycle; 305 if (step_diff) {
304 if (step_diff) { 306 lc8951_run(context, cycle);
305 lc8951_run(context, cycle);
306 }
307 } 307 }
308 } 308 }
309 } 309 }
310 310
311 void lc8951_write_byte(lc8951 *context, uint32_t cycle, int sector_offset, uint8_t byte) 311 void lc8951_write_byte(lc8951 *context, uint32_t cycle, int sector_offset, uint8_t byte)