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comparison genesis.c @ 1769:8fe162bdb038 mame_interp

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Merge from default
author Michael Pavone <pavone@retrodev.com>
date Fri, 01 Mar 2019 14:17:29 -0800
parents 95e387e1d63c 1dc718581aac
children 0a26f3657295
comparison
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1768:63256371046f 1769:8fe162bdb038
37 #define MAX_SOUND_CYCLES 1000 37 #define MAX_SOUND_CYCLES 1000
38 #else 38 #else
39 #define MAX_SOUND_CYCLES 100000 39 #define MAX_SOUND_CYCLES 100000
40 #endif 40 #endif
41 41
42 #ifdef NEW_CORE
43 #define Z80_CYCLE cycles
44 #define Z80_OPTS opts
45 #define z80_handle_code_write(...)
46 #else
47 #define Z80_CYCLE current_cycle
48 #define Z80_OPTS options
49 #endif
50
42 void genesis_serialize(genesis_context *gen, serialize_buffer *buf, uint32_t m68k_pc) 51 void genesis_serialize(genesis_context *gen, serialize_buffer *buf, uint32_t m68k_pc)
43 { 52 {
44 start_section(buf, SECTION_68000); 53 start_section(buf, SECTION_68000);
45 m68k_serialize(gen->m68k, m68k_pc, buf); 54 m68k_serialize(gen->m68k, m68k_pc, buf);
46 end_section(buf); 55 end_section(buf);
62 end_section(buf); 71 end_section(buf);
63 72
64 start_section(buf, SECTION_GEN_BUS_ARBITER); 73 start_section(buf, SECTION_GEN_BUS_ARBITER);
65 save_int8(buf, gen->z80->reset); 74 save_int8(buf, gen->z80->reset);
66 save_int8(buf, gen->z80->busreq); 75 save_int8(buf, gen->z80->busreq);
67 save_int16(buf, gen->z80->bank_reg); 76 save_int16(buf, gen->z80_bank_reg);
68 end_section(buf); 77 end_section(buf);
69 78
70 start_section(buf, SECTION_SEGA_IO_1); 79 start_section(buf, SECTION_SEGA_IO_1);
71 io_serialize(gen->io.ports, buf); 80 io_serialize(gen->io.ports, buf);
72 end_section(buf); 81 end_section(buf);
139 z80_invalidate_code_range(gen->z80, 0, 0x4000); 148 z80_invalidate_code_range(gen->z80, 0, 0x4000);
140 } 149 }
141 150
142 static void update_z80_bank_pointer(genesis_context *gen) 151 static void update_z80_bank_pointer(genesis_context *gen)
143 { 152 {
144 if (gen->z80->bank_reg < 0x140) { 153 if (gen->z80_bank_reg < 0x140) {
145 gen->z80->mem_pointers[1] = get_native_pointer(gen->z80->bank_reg << 15, (void **)gen->m68k->mem_pointers, &gen->m68k->options->gen); 154 gen->z80->mem_pointers[1] = get_native_pointer(gen->z80_bank_reg << 15, (void **)gen->m68k->mem_pointers, &gen->m68k->options->gen);
146 } else { 155 } else {
147 gen->z80->mem_pointers[1] = NULL; 156 gen->z80->mem_pointers[1] = NULL;
148 } 157 }
158 z80_invalidate_code_range(gen->z80, 0x8000, 0xFFFF);
149 } 159 }
150 160
151 static void bus_arbiter_deserialize(deserialize_buffer *buf, void *vgen) 161 static void bus_arbiter_deserialize(deserialize_buffer *buf, void *vgen)
152 { 162 {
153 genesis_context *gen = vgen; 163 genesis_context *gen = vgen;
154 gen->z80->reset = load_int8(buf); 164 gen->z80->reset = load_int8(buf);
155 gen->z80->busreq = load_int8(buf); 165 gen->z80->busreq = load_int8(buf);
156 gen->z80->bank_reg = load_int16(buf) & 0x1FF; 166 gen->z80_bank_reg = load_int16(buf) & 0x1FF;
157 } 167 }
158 168
159 static void adjust_int_cycle(m68k_context * context, vdp_context * v_context); 169 static void adjust_int_cycle(m68k_context * context, vdp_context * v_context);
160 void genesis_deserialize(deserialize_buffer *buf, genesis_context *gen) 170 void genesis_deserialize(deserialize_buffer *buf, genesis_context *gen)
161 { 171 {
287 #endif 297 #endif
288 298
289 static void z80_next_int_pulse(z80_context * z_context) 299 static void z80_next_int_pulse(z80_context * z_context)
290 { 300 {
291 genesis_context * gen = z_context->system; 301 genesis_context * gen = z_context->system;
292 vdp_run_context(gen->vdp, z_context->current_cycle); 302 #ifdef NEW_CORE
303 z_context->int_cycle = vdp_next_vint_z80(gen->vdp);
304 z_context->int_end_cycle = z_context->int_cycle + Z80_INT_PULSE_MCLKS;
305 z_context->int_value = 0xFF;
306 z80_sync_cycle(z_context, z_context->sync_cycle);
307 #else
293 z_context->int_pulse_start = vdp_next_vint_z80(gen->vdp); 308 z_context->int_pulse_start = vdp_next_vint_z80(gen->vdp);
294 z_context->int_pulse_end = z_context->int_pulse_start + Z80_INT_PULSE_MCLKS; 309 z_context->int_pulse_end = z_context->int_pulse_start + Z80_INT_PULSE_MCLKS;
295 z_context->im2_vector = 0xFF; 310 z_context->im2_vector = 0xFF;
311 #endif
296 } 312 }
297 313
298 static void sync_z80(z80_context * z_context, uint32_t mclks) 314 static void sync_z80(z80_context * z_context, uint32_t mclks)
299 { 315 {
300 #ifndef NO_Z80 316 #ifndef NO_Z80
301 if (z80_enabled) { 317 if (z80_enabled) {
318 #ifdef NEW_CORE
319 if (z_context->int_cycle == 0xFFFFFFFFU) {
320 z80_next_int_pulse(z_context);
321 }
322 #endif
302 z80_run(z_context, mclks); 323 z80_run(z_context, mclks);
303 } else 324 } else
304 #endif 325 #endif
305 { 326 {
306 z_context->current_cycle = mclks; 327 z_context->Z80_CYCLE = mclks;
307 } 328 }
308 } 329 }
309 330
310 static void sync_sound(genesis_context * gen, uint32_t target) 331 static void sync_sound(genesis_context * gen, uint32_t target)
311 { 332 {
412 if (address) { 433 if (address) {
413 if (gen->header.enter_debugger) { 434 if (gen->header.enter_debugger) {
414 gen->header.enter_debugger = 0; 435 gen->header.enter_debugger = 0;
415 debugger(context, address); 436 debugger(context, address);
416 } 437 }
438 #ifdef NEW_CORE
439 if (gen->header.save_state) {
440 #else
417 if (gen->header.save_state && (z_context->pc || !z_context->native_pc || z_context->reset || !z_context->busreq)) { 441 if (gen->header.save_state && (z_context->pc || !z_context->native_pc || z_context->reset || !z_context->busreq)) {
442 #endif
418 uint8_t slot = gen->header.save_state - 1; 443 uint8_t slot = gen->header.save_state - 1;
419 gen->header.save_state = 0; 444 gen->header.save_state = 0;
445 #ifndef NEW_CORE
420 if (z_context->native_pc && !z_context->reset) { 446 if (z_context->native_pc && !z_context->reset) {
421 //advance Z80 core to the start of an instruction 447 //advance Z80 core to the start of an instruction
422 while (!z_context->pc) 448 while (!z_context->pc)
423 { 449 {
424 sync_z80(z_context, z_context->current_cycle + MCLKS_PER_Z80); 450 sync_z80(z_context, z_context->current_cycle + MCLKS_PER_Z80);
425 } 451 }
426 } 452 }
453 #endif
427 char *save_path = slot == SERIALIZE_SLOT ? NULL : get_slot_name(&gen->header, slot, use_native_states ? "state" : "gst"); 454 char *save_path = slot == SERIALIZE_SLOT ? NULL : get_slot_name(&gen->header, slot, use_native_states ? "state" : "gst");
428 if (use_native_states || slot == SERIALIZE_SLOT) { 455 if (use_native_states || slot == SERIALIZE_SLOT) {
429 serialize_buffer state; 456 serialize_buffer state;
430 init_serialize(&state); 457 init_serialize(&state);
431 genesis_serialize(gen, &state, address); 458 genesis_serialize(gen, &state, address);
574 fatal_error("machine freeze due to write to Z80 address %X\n", 0x7F00 | vdp_port); 601 fatal_error("machine freeze due to write to Z80 address %X\n", 0x7F00 | vdp_port);
575 } 602 }
576 if (vdp_port < 0x10) { 603 if (vdp_port < 0x10) {
577 //These probably won't currently interact well with the 68K accessing the VDP 604 //These probably won't currently interact well with the 68K accessing the VDP
578 if (vdp_port < 4) { 605 if (vdp_port < 4) {
579 vdp_run_context(gen->vdp, context->current_cycle); 606 vdp_run_context(gen->vdp, context->Z80_CYCLE);
580 vdp_data_port_write(gen->vdp, value << 8 | value); 607 vdp_data_port_write(gen->vdp, value << 8 | value);
581 } else if (vdp_port < 8) { 608 } else if (vdp_port < 8) {
582 vdp_run_context_full(gen->vdp, context->current_cycle); 609 vdp_run_context_full(gen->vdp, context->Z80_CYCLE);
583 vdp_control_port_write(gen->vdp, value << 8 | value); 610 vdp_control_port_write(gen->vdp, value << 8 | value);
584 } else { 611 } else {
585 fatal_error("Illegal write to HV Counter port %X\n", vdp_port); 612 fatal_error("Illegal write to HV Counter port %X\n", vdp_port);
586 } 613 }
587 } else if (vdp_port < 0x18) { 614 } else if (vdp_port < 0x18) {
588 sync_sound(gen, context->current_cycle); 615 sync_sound(gen, context->Z80_CYCLE);
589 psg_write(gen->psg, value); 616 psg_write(gen->psg, value);
590 } else { 617 } else {
591 vdp_test_port_write(gen->vdp, value); 618 vdp_test_port_write(gen->vdp, value);
592 } 619 }
593 return context; 620 return context;
662 fatal_error("machine freeze due to read from Z80 address %X\n", 0x7F00 | vdp_port); 689 fatal_error("machine freeze due to read from Z80 address %X\n", 0x7F00 | vdp_port);
663 } 690 }
664 genesis_context * gen = context->system; 691 genesis_context * gen = context->system;
665 //VDP access goes over the 68K bus like a bank area access 692 //VDP access goes over the 68K bus like a bank area access
666 //typical delay from bus arbitration 693 //typical delay from bus arbitration
667 context->current_cycle += 3 * MCLKS_PER_Z80; 694 context->Z80_CYCLE += 3 * MCLKS_PER_Z80;
668 //TODO: add cycle for an access right after a previous one 695 //TODO: add cycle for an access right after a previous one
669 //TODO: Below cycle time is an estimate based on the time between 68K !BG goes low and Z80 !MREQ goes high 696 //TODO: Below cycle time is an estimate based on the time between 68K !BG goes low and Z80 !MREQ goes high
670 // Needs a new logic analyzer capture to get the actual delay on the 68K side 697 // Needs a new logic analyzer capture to get the actual delay on the 68K side
671 gen->m68k->current_cycle += 8 * MCLKS_PER_68K; 698 gen->m68k->current_cycle += 8 * MCLKS_PER_68K;
672 699
673 700
674 vdp_port &= 0x1F; 701 vdp_port &= 0x1F;
675 uint16_t ret; 702 uint16_t ret;
676 if (vdp_port < 0x10) { 703 if (vdp_port < 0x10) {
677 //These probably won't currently interact well with the 68K accessing the VDP 704 //These probably won't currently interact well with the 68K accessing the VDP
678 vdp_run_context(gen->vdp, context->current_cycle); 705 vdp_run_context(gen->vdp, context->Z80_CYCLE);
679 if (vdp_port < 4) { 706 if (vdp_port < 4) {
680 ret = vdp_data_port_read(gen->vdp); 707 ret = vdp_data_port_read(gen->vdp);
681 } else if (vdp_port < 8) { 708 } else if (vdp_port < 8) {
682 ret = vdp_control_port_read(gen->vdp); 709 ret = vdp_control_port_read(gen->vdp);
683 } else { 710 } else {
714 ym_address_write_part2(gen->ym, value); 741 ym_address_write_part2(gen->ym, value);
715 } else { 742 } else {
716 ym_address_write_part1(gen->ym, value); 743 ym_address_write_part1(gen->ym, value);
717 } 744 }
718 } else if (location == 0x6000) { 745 } else if (location == 0x6000) {
719 gen->z80->bank_reg = (gen->z80->bank_reg >> 1 | value << 8) & 0x1FF; 746 gen->z80_bank_reg = (gen->z80_bank_reg >> 1 | value << 8) & 0x1FF;
720 if (gen->z80->bank_reg < 0x80) { 747 if (gen->z80_bank_reg < 0x80) {
721 gen->z80->mem_pointers[1] = (gen->z80->bank_reg << 15) + ((char *)gen->z80->mem_pointers[2]); 748 gen->z80->mem_pointers[1] = (gen->z80_bank_reg << 15) + ((char *)gen->z80->mem_pointers[2]);
722 } else { 749 } else {
723 gen->z80->mem_pointers[1] = NULL; 750 gen->z80->mem_pointers[1] = NULL;
724 } 751 }
725 } else { 752 } else {
726 fatal_error("68K write to unhandled Z80 address %X\n", location); 753 fatal_error("68K write to unhandled Z80 address %X\n", location);
945 972
946 static void * z80_write_ym(uint32_t location, void * vcontext, uint8_t value) 973 static void * z80_write_ym(uint32_t location, void * vcontext, uint8_t value)
947 { 974 {
948 z80_context * context = vcontext; 975 z80_context * context = vcontext;
949 genesis_context * gen = context->system; 976 genesis_context * gen = context->system;
950 sync_sound(gen, context->current_cycle); 977 sync_sound(gen, context->Z80_CYCLE);
951 if (location & 1) { 978 if (location & 1) {
952 ym_data_write(gen->ym, value); 979 ym_data_write(gen->ym, value);
953 } else if (location & 2) { 980 } else if (location & 2) {
954 ym_address_write_part2(gen->ym, value); 981 ym_address_write_part2(gen->ym, value);
955 } else { 982 } else {
960 987
961 static uint8_t z80_read_ym(uint32_t location, void * vcontext) 988 static uint8_t z80_read_ym(uint32_t location, void * vcontext)
962 { 989 {
963 z80_context * context = vcontext; 990 z80_context * context = vcontext;
964 genesis_context * gen = context->system; 991 genesis_context * gen = context->system;
965 sync_sound(gen, context->current_cycle); 992 sync_sound(gen, context->Z80_CYCLE);
966 return ym_read_status(gen->ym); 993 return ym_read_status(gen->ym);
967 } 994 }
968 995
969 static uint8_t z80_read_bank(uint32_t location, void * vcontext) 996 static uint8_t z80_read_bank(uint32_t location, void * vcontext)
970 { 997 {
971 z80_context * context = vcontext; 998 z80_context * context = vcontext;
972 genesis_context *gen = context->system; 999 genesis_context *gen = context->system;
973 1000
974 if (gen->bus_busy) { 1001 if (gen->bus_busy) {
975 #ifdef USE_NATIVE 1002 #if defined(USE_NATIVE) || defined(NEW_CORE)
976 context->current_cycle = context->sync_cycle; 1003 context->Z80_CYCLE = gen->m68k->current_cycle;
977 #else 1004 #else
978 context->m_icount = 0; 1005 context->m_icount = 0;
979 #endif 1006 #endif
980 } 1007 }
981 1008
982 //typical delay from bus arbitration 1009 //typical delay from bus arbitration
983 #ifdef USE_NATIVE 1010 #if defined(USE_NATIVE) || defined(NEW_CORE)
984 context->current_cycle += 3 * MCLKS_PER_Z80; 1011 context->Z80_CYCLE += 3 * MCLKS_PER_Z80;
985 #else 1012 #else
986 context->m_icount -= 3; 1013 context->m_icount -= 3;
987 #endif 1014 #endif
988 //TODO: add cycle for an access right after a previous one 1015 //TODO: add cycle for an access right after a previous one
989 //TODO: Below cycle time is an estimate based on the time between 68K !BG goes low and Z80 !MREQ goes high 1016 //TODO: Below cycle time is an estimate based on the time between 68K !BG goes low and Z80 !MREQ goes high
992 1019
993 location &= 0x7FFF; 1020 location &= 0x7FFF;
994 if (context->mem_pointers[1]) { 1021 if (context->mem_pointers[1]) {
995 return context->mem_pointers[1][location ^ 1]; 1022 return context->mem_pointers[1][location ^ 1];
996 } 1023 }
997 uint32_t address = context->bank_reg << 15 | location; 1024 uint32_t address = gen->z80_bank_reg << 15 | location;
998 if (address >= 0xC00000 && address < 0xE00000) { 1025 if (address >= 0xC00000 && address < 0xE00000) {
999 return z80_vdp_port_read(location & 0xFF, context); 1026 return z80_vdp_port_read(location & 0xFF, context);
1000 } else { 1027 } else {
1001 fprintf(stderr, "Unhandled read by Z80 from address %X through banked memory area (%X)\n", address, context->bank_reg << 15); 1028 fprintf(stderr, "Unhandled read by Z80 from address %X through banked memory area (%X)\n", address, gen->z80_bank_reg << 15);
1002 } 1029 }
1003 return 0; 1030 return 0;
1004 } 1031 }
1005 1032
1006 static void *z80_write_bank(uint32_t location, void * vcontext, uint8_t value) 1033 static void *z80_write_bank(uint32_t location, void * vcontext, uint8_t value)
1007 { 1034 {
1008 z80_context * context = vcontext; 1035 z80_context * context = vcontext;
1009 genesis_context *gen = context->system; 1036 genesis_context *gen = context->system;
1010 if (gen->bus_busy) { 1037 if (gen->bus_busy) {
1011 #ifdef USE_NATIVE 1038 #if defined(USE_NATIVE) || defined(NEW_CORE)
1012 context->current_cycle = context->sync_cycle; 1039 context->Z80_CYCLE = gen->m68k->current_cycle;
1013 #else 1040 #else
1014 context->m_icount = 0; 1041 context->m_icount = 0;
1015 #endif 1042 #endif
1016 } 1043 }
1017 //typical delay from bus arbitration 1044 //typical delay from bus arbitration
1018 #ifdef USE_NATIVE 1045 #if defined(USE_NATIVE) || defined(NEW_CORE)
1019 context->current_cycle += 3 * MCLKS_PER_Z80; 1046 context->Z80_CYCLE += 3 * MCLKS_PER_Z80;
1020 #else 1047 #else
1021 context->m_icount -= 3; 1048 context->m_icount -= 3;
1022 #endif 1049 #endif
1023 //TODO: add cycle for an access right after a previous one 1050 //TODO: add cycle for an access right after a previous one
1024 //TODO: Below cycle time is an estimate based on the time between 68K !BG goes low and Z80 !MREQ goes high 1051 //TODO: Below cycle time is an estimate based on the time between 68K !BG goes low and Z80 !MREQ goes high
1025 // Needs a new logic analyzer capture to get the actual delay on the 68K side 1052 // Needs a new logic analyzer capture to get the actual delay on the 68K side
1026 gen->m68k->current_cycle += 8 * MCLKS_PER_68K; 1053 gen->m68k->current_cycle += 8 * MCLKS_PER_68K;
1027 1054
1028 location &= 0x7FFF; 1055 location &= 0x7FFF;
1029 uint32_t address = context->bank_reg << 15 | location; 1056 uint32_t address = gen->z80_bank_reg << 15 | location;
1030 if (address >= 0xE00000) { 1057 if (address >= 0xE00000) {
1031 address &= 0xFFFF; 1058 address &= 0xFFFF;
1032 ((uint8_t *)gen->work_ram)[address ^ 1] = value; 1059 ((uint8_t *)gen->work_ram)[address ^ 1] = value;
1033 } else if (address >= 0xC00000) { 1060 } else if (address >= 0xC00000) {
1034 z80_vdp_port_write(location & 0xFF, context, value); 1061 z80_vdp_port_write(location & 0xFF, context, value);
1039 } 1066 }
1040 1067
1041 static void *z80_write_bank_reg(uint32_t location, void * vcontext, uint8_t value) 1068 static void *z80_write_bank_reg(uint32_t location, void * vcontext, uint8_t value)
1042 { 1069 {
1043 z80_context * context = vcontext; 1070 z80_context * context = vcontext;
1044 1071 genesis_context *gen = context->system;
1045 context->bank_reg = (context->bank_reg >> 1 | value << 8) & 0x1FF; 1072
1073 gen->z80_bank_reg = (gen->z80_bank_reg >> 1 | value << 8) & 0x1FF;
1046 update_z80_bank_pointer(context->system); 1074 update_z80_bank_pointer(context->system);
1047 1075
1048 return context; 1076 return context;
1049 } 1077 }
1050 1078
1271 memmap_chunk *map = (memmap_chunk *)gen->m68k->options->gen.memmap; 1299 memmap_chunk *map = (memmap_chunk *)gen->m68k->options->gen.memmap;
1272 m68k_options_free(gen->m68k->options); 1300 m68k_options_free(gen->m68k->options);
1273 free(gen->cart); 1301 free(gen->cart);
1274 free(gen->m68k); 1302 free(gen->m68k);
1275 free(gen->work_ram); 1303 free(gen->work_ram);
1276 z80_options_free(gen->z80->options); 1304 z80_options_free(gen->z80->Z80_OPTS);
1277 free(gen->z80); 1305 free(gen->z80);
1278 free(gen->zram); 1306 free(gen->zram);
1279 ym_free(gen->ym); 1307 ym_free(gen->ym);
1280 psg_free(gen->psg); 1308 psg_free(gen->psg);
1281 free(gen->header.save_dir); 1309 free(gen->header.save_dir);
1399 z80_map[0].buffer = gen->zram = calloc(1, Z80_RAM_BYTES); 1427 z80_map[0].buffer = gen->zram = calloc(1, Z80_RAM_BYTES);
1400 #ifndef NO_Z80 1428 #ifndef NO_Z80
1401 z80_options *z_opts = malloc(sizeof(z80_options)); 1429 z80_options *z_opts = malloc(sizeof(z80_options));
1402 init_z80_opts(z_opts, z80_map, 5, NULL, 0, MCLKS_PER_Z80, 0xFFFF); 1430 init_z80_opts(z_opts, z80_map, 5, NULL, 0, MCLKS_PER_Z80, 0xFFFF);
1403 gen->z80 = init_z80_context(z_opts); 1431 gen->z80 = init_z80_context(z_opts);
1432 #ifndef NEW_CORE
1404 gen->z80->next_int_pulse = z80_next_int_pulse; 1433 gen->z80->next_int_pulse = z80_next_int_pulse;
1434 #endif
1405 z80_assert_reset(gen->z80, 0); 1435 z80_assert_reset(gen->z80, 0);
1406 #else 1436 #else
1407 gen->z80 = calloc(1, sizeof(z80_context)); 1437 gen->z80 = calloc(1, sizeof(z80_context));
1408 #endif 1438 #endif
1409 1439