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comparison m68k_to_x86.c @ 107:9705075fcf36

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Fix areg indexed mode for move dst
author Mike Pavone <pavone@retrodev.com>
date Fri, 28 Dec 2012 14:30:25 -0800
parents 1eba2b9455f8
children a575808dd90b
comparison
equal deleted inserted replaced
106:1eba2b9455f8 107:9705075fcf36
824 break; 824 break;
825 } 825 }
826 break; 826 break;
827 case MODE_AREG_INDEX_DISP8: 827 case MODE_AREG_INDEX_DISP8:
828 dst = cycles(dst, 6);//TODO: Check to make sure this is correct 828 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
829 if (opts->aregs[inst->src.params.regs.pri] >= 0) { 829 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
830 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D); 830 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
831 } else { 831 } else {
832 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D); 832 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
833 } 833 }
834 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; 834 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
835 if (inst->src.params.regs.sec & 1) { 835 if (inst->dst.params.regs.sec & 1) {
836 if (inst->src.params.regs.sec & 0x10) { 836 if (inst->dst.params.regs.sec & 0x10) {
837 if (opts->aregs[sec_reg] >= 0) { 837 if (opts->aregs[sec_reg] >= 0) {
838 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); 838 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
839 } else { 839 } else {
840 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); 840 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
841 } 841 }
848 } 848 }
849 } else { 849 } else {
850 if (src.base == SCRATCH1) { 850 if (src.base == SCRATCH1) {
851 dst = push_r(dst, SCRATCH1); 851 dst = push_r(dst, SCRATCH1);
852 } 852 }
853 if (inst->src.params.regs.sec & 0x10) { 853 if (inst->dst.params.regs.sec & 0x10) {
854 if (opts->aregs[sec_reg] >= 0) { 854 if (opts->aregs[sec_reg] >= 0) {
855 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); 855 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
856 } else { 856 } else {
857 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); 857 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
858 } 858 }
866 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); 866 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
867 if (src.base == SCRATCH1) { 867 if (src.base == SCRATCH1) {
868 dst = pop_r(dst, SCRATCH1); 868 dst = pop_r(dst, SCRATCH1);
869 } 869 }
870 } 870 }
871 if (inst->src.params.regs.displacement) { 871 if (inst->dst.params.regs.displacement) {
872 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D); 872 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
873 } 873 }
874 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size); 874 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
875 dst = setcc_r(dst, CC_Z, FLAG_Z); 875 dst = setcc_r(dst, CC_Z, FLAG_Z);
876 dst = setcc_r(dst, CC_S, FLAG_N); 876 dst = setcc_r(dst, CC_S, FLAG_N);
877 switch (inst->extra.size) 877 switch (inst->extra.size)