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comparison cpu_dsl.py @ 2611:9bd90cd94000

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Fix asr and lsr in new 68K core
author Michael Pavone <pavone@retrodev.com>
date Sat, 15 Feb 2025 23:06:49 -0800
parents 2de52352936c
children cbd54de385d3
comparison
equal deleted inserted replaced
2610:2de52352936c 2611:9bd90cd94000
644 else: 644 else:
645 output.append('\n\t{reg} = {res} & {mask};'.format(reg=reg, res=myRes, mask = mask)) 645 output.append('\n\t{reg} = {res} & {mask};'.format(reg=reg, res=myRes, mask = mask))
646 if after: 646 if after:
647 output.append(after) 647 output.append(after)
648 elif calc == 'zero': 648 elif calc == 'zero':
649 if prog.carryFlowDst: 649 realSize = prog.getLastSize()
650 realSize = prog.getLastSize() 650 if realSize != prog.paramSize(lastDst):
651 output.append(f'\n\t//realSize = {realSize}, carryFlowDst size = {prog.paramSize(prog.carryFlowDst)}, carryFLowDst = {prog.carryFlowDst}') 651 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1)
652 if realSize != prog.paramSize(prog.carryFlowDst):
653 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1)
654 if type(storage) is tuple: 652 if type(storage) is tuple:
655 reg,storageBit = storage 653 reg,storageBit = storage
656 reg = prog.resolveParam(reg, None, {}) 654 reg = prog.resolveParam(reg, None, {})
657 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} | {bit}U);'.format( 655 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} | {bit}U);'.format(
658 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit 656 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
791 dst = prog.carryFlowDst = name 789 dst = prog.carryFlowDst = name
792 prog.lastA = params[0] 790 prog.lastA = params[0]
793 prog.lastB = params[1] 791 prog.lastB = params[1]
794 if needsSizeAdjust: 792 if needsSizeAdjust:
795 sizeMask = (1 << size) - 1 793 sizeMask = (1 << size) - 1
796 return decl + '\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);'.format( 794 return decl + '\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) | (({a} & {mask}) && {b} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);'.format(
797 name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask) 795 name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask)
798 elif needsSizeAdjust: 796 elif needsSizeAdjust:
799 decl,name = prog.getTemp(size) 797 decl,name = prog.getTemp(size)
800 sizeMask = (1 << size) - 1 798 sizeMask = (1 << size) - 1
801 return decl + ('\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);' + 799 return decl + ('\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) | (({a} & {mask}) && {b} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);' +
802 '\n\t{dst} = ({dst} & ~{sizeMask}) | {name};').format( 800 '\n\t{dst} = ({dst} & ~{sizeMask}) | {name};').format(
803 name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask) 801 name = name, a = params[0], b = params[1], dst = params[2], mask = mask, size=size, sizeMask=sizeMask)
804 else: 802 else:
805 dst = params[2] 803 dst = params[2]
806 804
807 return decl + '\n\t{dst} = ({a} >> {b}) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format( 805 return decl + '\n\t{dst} = ({a} >> {b}) | (({a} & {mask}) && {b} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format(
808 a = params[0], b = params[1], dst = dst, mask = mask, size=size) 806 a = params[0], b = params[1], dst = dst, mask = mask, size=size)
809 807
810 def _sext(size, src): 808 def _sext(size, src):
811 if size == 16: 809 if size == 16:
812 return src | 0xFF00 if src & 0x80 else src & 0x7F 810 return src | 0xFF00 if src & 0x80 else src & 0x7F