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comparison m68k.cpu @ 2611:9bd90cd94000

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Fix asr and lsr in new 68K core
author Michael Pavone <pavone@retrodev.com>
date Sat, 15 Feb 2025 23:06:49 -0800
parents 2de52352936c
children 1579b840a1af
comparison
equal deleted inserted replaced
2610:2de52352936c 2611:9bd90cd94000
1440 1440
1441 1110CCC0ZZ101RRR lsr_dn 1441 1110CCC0ZZ101RRR lsr_dn
1442 invalid Z 3 1442 invalid Z 3
1443 local shift 8 1443 local shift 8
1444 and dregs.C 63 shift 1444 and dregs.C 63 shift
1445 lsr dregs.R shift dregs.R Z 1445 switch Z
1446 update_flags XNZV0C 1446 case 2
1447 if shift >=U 32
1448 if shift = 32
1449 lsr dregs.R 31 dregs.R Z
1450 lsr dregs.R 1 dregs.R Z
1451 update_flags XN0Z1V0C
1452 else
1453 dregs.R:Z = 0
1454 update_flags X0N0Z1V0C0
1455 end
1456 else
1457 lsr dregs.R shift dregs.R Z
1458 update_flags NZV0C
1459 if shift
1460 xflag = cflag
1461 end
1462 end
1463 case 1
1464 if shift >=U 16
1465 if shift = 16
1466 lsr dregs.R 15 dregs.R Z
1467 lsr dregs.R 1 dregs.R Z
1468 update_flags XN0Z1V0C
1469 else
1470 dregs.R:Z = 0
1471 update_flags X0N0Z1V0C0
1472 end
1473 else
1474 lsr dregs.R shift dregs.R Z
1475 update_flags NZV0C
1476 if shift
1477 xflag = cflag
1478 end
1479 end
1480 case 0
1481 if shift >=U 8
1482 if shift = 8
1483 lsr dregs.R 7 dregs.R Z
1484 lsr dregs.R 1 dregs.R Z
1485 update_flags XN0Z1V0C
1486 else
1487 dregs.R:Z = 0
1488 update_flags X0N0Z1V0C0
1489 end
1490 else
1491 lsr dregs.R shift dregs.R Z
1492 update_flags NZV0C
1493 if shift
1494 xflag = cflag
1495 end
1496 end
1497 end
1447 add shift shift shift 1498 add shift shift shift
1448 switch Z 1499 switch Z
1449 case 2 1500 case 2
1450 add 4 shift shift 1501 add 4 shift shift
1451 default 1502 default
1494 m68k_prefetch 1545 m68k_prefetch
1495 1546
1496 1110CCC0ZZ100RRR asr_dn 1547 1110CCC0ZZ100RRR asr_dn
1497 invalid Z 3 1548 invalid Z 3
1498 local shift 32 1549 local shift 32
1499 local shift_cycles 32
1500 and dregs.C 63 shift 1550 and dregs.C 63 shift
1501 shift_cycles = shift 1551 switch Z
1502 if shift = 0 1552 case 2
1503 cmp 0 dregs.R Z 1553 if shift >=U 32
1504 update_flags NZV0C0 1554 asr dregs.R 31 dregs.R Z
1505 else 1555 asr dregs.R 1 dregs.R Z
1506 switch Z 1556 update_flags NZV0
1507 case 0 1557 cflag = nflag
1508 if shift >=U 9 1558 xflag = nflag
1509 shift = 8 1559 else
1560 asr dregs.R shift dregs.R Z
1561 update_flags NZV0C
1562 if shift
1563 xflag = cflag
1510 end 1564 end
1511 case 1 1565 end
1512 if shift >=U 17 1566 case 1
1513 shift = 16 1567 if shift >=U 16
1568 asr dregs.R 15 dregs.R Z
1569 asr dregs.R 1 dregs.R Z
1570 update_flags NZV0
1571 cflag = nflag
1572 xflag = nflag
1573 else
1574 asr dregs.R shift dregs.R Z
1575 update_flags NZV0C
1576 if shift
1577 xflag = cflag
1514 end 1578 end
1515 case 2 1579 end
1516 if shift >=U 33 1580 case 0
1517 shift = 32 1581 if shift >=U 8
1582 asr dregs.R 7 dregs.R Z
1583 asr dregs.R 1 dregs.R Z
1584 update_flags NZV0
1585 cflag = nflag
1586 xflag = nflag
1587 else
1588 asr dregs.R shift dregs.R Z
1589 update_flags NZV0C
1590 if shift
1591 xflag = cflag
1518 end 1592 end
1519 end 1593 end
1520 asr dregs.R shift dregs.R Z 1594 end
1521 update_flags XNZV0C 1595 shift += shift
1522 end 1596 switch Z
1523 shift_cycles += shift_cycles 1597 case 2
1524 switch Z 1598 shift += 4
1525 case 2 1599 default
1526 shift_cycles += 4 1600 shift += 2
1527 default 1601 end
1528 shift_cycles += 2 1602 cycles shift
1529 end
1530 cycles shift_cycles
1531 #TODO: should this happen before or after the majority of the shift? 1603 #TODO: should this happen before or after the majority of the shift?
1532 m68k_prefetch 1604 m68k_prefetch
1533 1605
1534 1110000011MMMRRR asr_ea 1606 1110000011MMMRRR asr_ea
1535 invalid M 0 1607 invalid M 0