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comparison backend_x86.c @ 2134:9caebcfeac72

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Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
author Michael Pavone <pavone@retrodev.com>
date Fri, 18 Mar 2022 20:49:07 -0700
parents 8554751f17b5
children b6338e18787e
comparison
equal deleted inserted replaced
2133:8554751f17b5 2134:9caebcfeac72
162 max_address = memmap[chunk].start; 162 max_address = memmap[chunk].start;
163 } 163 }
164 164
165 if (memmap[chunk].mask != opts->address_mask) { 165 if (memmap[chunk].mask != opts->address_mask) {
166 and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size); 166 and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size);
167 }
168 code_ptr after_normal = NULL;
169 if (size == SZ_B && memmap[chunk].shift != 0) {
170 btr_ir(code, 0, adr_reg, opts->address_size);
171 code_ptr normal = code->cur+1;
172 jcc(code, CC_NC, normal);
173 if (memmap[chunk].shift > 0) {
174 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size);
175 } else {
176 shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size);
177 }
178 or_ir(code, 1, adr_reg, opts->address_size);
179 after_normal = code->cur + 1;
180 jmp(code, after_normal);
181 *normal = code->cur - (normal + 1);
182 }
183 if (memmap[chunk].shift > 0) {
184 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size);
185 } else if (memmap[chunk].shift < 0) {
186 shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size);
187 }
188 if (after_normal) {
189 *after_normal = code->cur - (after_normal + 1);
167 } 190 }
168 void * cfun; 191 void * cfun;
169 switch (fun_type) 192 switch (fun_type)
170 { 193 {
171 case READ_16: 194 case READ_16: