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comparison genesis.c @ 2134:9caebcfeac72

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Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
author Michael Pavone <pavone@retrodev.com>
date Fri, 18 Mar 2022 20:49:07 -0700
parents 00b6592cad42
children a418fa599b2e
comparison
equal deleted inserted replaced
2133:8554751f17b5 2134:9caebcfeac72
1797 } 1797 }
1798 1798
1799 static genesis_context *shared_init(uint32_t system_opts, rom_info *rom, uint8_t force_region) 1799 static genesis_context *shared_init(uint32_t system_opts, rom_info *rom, uint8_t force_region)
1800 { 1800 {
1801 static memmap_chunk z80_map[] = { 1801 static memmap_chunk z80_map[] = {
1802 { 0x0000, 0x4000, 0x1FFF, 0, 0, MMAP_READ | MMAP_WRITE | MMAP_CODE, NULL, NULL, NULL, NULL, NULL }, 1802 { 0x0000, 0x4000, 0x1FFF, .flags = MMAP_READ | MMAP_WRITE | MMAP_CODE},
1803 { 0x8000, 0x10000, 0x7FFF, 0, 0, 0, NULL, NULL, NULL, z80_read_bank, z80_write_bank}, 1803 { 0x8000, 0x10000, 0x7FFF, .read_8 = z80_read_bank, .write_8 = z80_write_bank},
1804 { 0x4000, 0x6000, 0x0003, 0, 0, 0, NULL, NULL, NULL, z80_read_ym, z80_write_ym}, 1804 { 0x4000, 0x6000, 0x0003, .read_8 = z80_read_ym, .write_8 = z80_write_ym},
1805 { 0x6000, 0x6100, 0xFFFF, 0, 0, 0, NULL, NULL, NULL, NULL, z80_write_bank_reg}, 1805 { 0x6000, 0x6100, 0xFFFF, .write_8 = z80_write_bank_reg},
1806 { 0x7F00, 0x8000, 0x00FF, 0, 0, 0, NULL, NULL, NULL, z80_vdp_port_read, z80_vdp_port_write} 1806 { 0x7F00, 0x8000, 0x00FF, .read_8 = z80_vdp_port_read, .write_8 = z80_vdp_port_write}
1807 }; 1807 };
1808 1808
1809 char *m68k_divider = tern_find_path(config, "clocks\0m68k_divider\0", TVAL_PTR).ptrval; 1809 char *m68k_divider = tern_find_path(config, "clocks\0m68k_divider\0", TVAL_PTR).ptrval;
1810 if (!m68k_divider) { 1810 if (!m68k_divider) {
1811 m68k_divider = "7"; 1811 m68k_divider = "7";
1924 1924
1925 return gen; 1925 return gen;
1926 } 1926 }
1927 1927
1928 static memmap_chunk base_map[] = { 1928 static memmap_chunk base_map[] = {
1929 {0xE00000, 0x1000000, 0xFFFF, 0, 0, MMAP_READ | MMAP_WRITE | MMAP_CODE, NULL, 1929 {0xE00000, 0x1000000, 0xFFFF, .flags = MMAP_READ | MMAP_WRITE | MMAP_CODE},
1930 NULL, NULL, NULL, NULL}, 1930 {0xC00000, 0xE00000, 0x1FFFFF, .read_16 = (read_16_fun)vdp_port_read, .write_16 =(write_16_fun)vdp_port_write,
1931 {0xC00000, 0xE00000, 0x1FFFFF, 0, 0, 0, NULL, 1931 .read_8 = (read_8_fun)vdp_port_read_b, .write_8 = (write_8_fun)vdp_port_write_b},
1932 (read_16_fun)vdp_port_read, (write_16_fun)vdp_port_write, 1932 {0xA00000, 0xA12000, 0x1FFFF, .read_16 = (read_16_fun)io_read_w, .write_16 = (write_16_fun)io_write_w,
1933 (read_8_fun)vdp_port_read_b, (write_8_fun)vdp_port_write_b}, 1933 .read_8 = (read_8_fun)io_read, .write_8 = (write_8_fun)io_write},
1934 {0xA00000, 0xA12000, 0x1FFFF, 0, 0, 0, NULL, 1934 {0x000000, 0xFFFFFF, 0xFFFFFF, .read_16 = (read_16_fun)unused_read, .write_16 = unused_write,
1935 (read_16_fun)io_read_w, (write_16_fun)io_write_w, 1935 .read_8 = (read_8_fun)unused_read_b, .write_8 = (write_8_fun)unused_write_b}
1936 (read_8_fun)io_read, (write_8_fun)io_write},
1937 {0x000000, 0xFFFFFF, 0xFFFFFF, 0, 0, 0, NULL,
1938 (read_16_fun)unused_read, (write_16_fun)unused_write,
1939 (read_8_fun)unused_read_b, (write_8_fun)unused_write_b}
1940 }; 1936 };
1941 const size_t base_chunks = sizeof(base_map)/sizeof(*base_map); 1937 const size_t base_chunks = sizeof(base_map)/sizeof(*base_map);
1942 1938
1943 genesis_context *alloc_config_genesis(void *rom, uint32_t rom_size, void *lock_on, uint32_t lock_on_size, uint32_t ym_opts, uint8_t force_region) 1939 genesis_context *alloc_config_genesis(void *rom, uint32_t rom_size, void *lock_on, uint32_t lock_on_size, uint32_t ym_opts, uint8_t force_region)
1944 { 1940 {