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comparison m68k_core_x86.c @ 581:9f40aa5243c2

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Combine implementations of lea and pea. Update bit instructions to use the op_ family of functions to simplify their implementation a bit.
author Michael Pavone <pavone@retrodev.com>
date Wed, 05 Mar 2014 19:26:53 -0800
parents 5157bc966c1a
children c05fcbfe1b1a
comparison
equal deleted inserted replaced
580:5157bc966c1a 581:9f40aa5243c2
1298 switch (inst->op) 1298 switch (inst->op)
1299 { 1299 {
1300 case M68K_ADD: add_ir(code, val, dst, size); break; 1300 case M68K_ADD: add_ir(code, val, dst, size); break;
1301 case M68K_ADDX: adc_ir(code, val, dst, size); break; 1301 case M68K_ADDX: adc_ir(code, val, dst, size); break;
1302 case M68K_AND: and_ir(code, val, dst, size); break; 1302 case M68K_AND: and_ir(code, val, dst, size); break;
1303 case M68K_BTST: bt_ir(code, val, dst, size); break;
1304 case M68K_BSET: bts_ir(code, val, dst, size); break;
1305 case M68K_BCLR: btr_ir(code, val, dst, size); break;
1306 case M68K_BCHG: btc_ir(code, val, dst, size); break;
1303 case M68K_EOR: xor_ir(code, val, dst, size); break; 1307 case M68K_EOR: xor_ir(code, val, dst, size); break;
1304 case M68K_OR: or_ir(code, val, dst, size); break; 1308 case M68K_OR: or_ir(code, val, dst, size); break;
1305 case M68K_ROL: rol_ir(code, val, dst, size); break; 1309 case M68K_ROL: rol_ir(code, val, dst, size); break;
1306 case M68K_ROR: ror_ir(code, val, dst, size); break; 1310 case M68K_ROR: ror_ir(code, val, dst, size); break;
1307 case M68K_ROXL: rcl_ir(code, val, dst, size); break; 1311 case M68K_ROXL: rcl_ir(code, val, dst, size); break;
1316 switch (inst->op) 1320 switch (inst->op)
1317 { 1321 {
1318 case M68K_ADD: add_irdisp(code, val, dst, disp, size); break; 1322 case M68K_ADD: add_irdisp(code, val, dst, disp, size); break;
1319 case M68K_ADDX: adc_irdisp(code, val, dst, disp, size); break; 1323 case M68K_ADDX: adc_irdisp(code, val, dst, disp, size); break;
1320 case M68K_AND: and_irdisp(code, val, dst, disp, size); break; 1324 case M68K_AND: and_irdisp(code, val, dst, disp, size); break;
1325 case M68K_BTST: bt_irdisp(code, val, dst, disp, size); break;
1326 case M68K_BSET: bts_irdisp(code, val, dst, disp, size); break;
1327 case M68K_BCLR: btr_irdisp(code, val, dst, disp, size); break;
1328 case M68K_BCHG: btc_irdisp(code, val, dst, disp, size); break;
1321 case M68K_EOR: xor_irdisp(code, val, dst, disp, size); break; 1329 case M68K_EOR: xor_irdisp(code, val, dst, disp, size); break;
1322 case M68K_OR: or_irdisp(code, val, dst, disp, size); break; 1330 case M68K_OR: or_irdisp(code, val, dst, disp, size); break;
1323 case M68K_ROL: rol_irdisp(code, val, dst, disp, size); break; 1331 case M68K_ROL: rol_irdisp(code, val, dst, disp, size); break;
1324 case M68K_ROR: ror_irdisp(code, val, dst, disp, size); break; 1332 case M68K_ROR: ror_irdisp(code, val, dst, disp, size); break;
1325 case M68K_ROXL: rcl_irdisp(code, val, dst, disp, size); break; 1333 case M68K_ROXL: rcl_irdisp(code, val, dst, disp, size); break;
1334 switch (inst->op) 1342 switch (inst->op)
1335 { 1343 {
1336 case M68K_ADD: add_rr(code, src, dst, size); break; 1344 case M68K_ADD: add_rr(code, src, dst, size); break;
1337 case M68K_ADDX: adc_rr(code, src, dst, size); break; 1345 case M68K_ADDX: adc_rr(code, src, dst, size); break;
1338 case M68K_AND: and_rr(code, src, dst, size); break; 1346 case M68K_AND: and_rr(code, src, dst, size); break;
1347 case M68K_BTST: bt_rr(code, src, dst, size); break;
1348 case M68K_BSET: bts_rr(code, src, dst, size); break;
1349 case M68K_BCLR: btr_rr(code, src, dst, size); break;
1350 case M68K_BCHG: btc_rr(code, src, dst, size); break;
1339 case M68K_EOR: xor_rr(code, src, dst, size); break; 1351 case M68K_EOR: xor_rr(code, src, dst, size); break;
1340 case M68K_OR: or_rr(code, src, dst, size); break; 1352 case M68K_OR: or_rr(code, src, dst, size); break;
1341 case M68K_SUB: sub_rr(code, src, dst, size); break; 1353 case M68K_SUB: sub_rr(code, src, dst, size); break;
1342 case M68K_SUBX: sbb_rr(code, src, dst, size); break; 1354 case M68K_SUBX: sbb_rr(code, src, dst, size); break;
1343 } 1355 }
1348 switch (inst->op) 1360 switch (inst->op)
1349 { 1361 {
1350 case M68K_ADD: add_rrdisp(code, src, dst, disp, size); break; 1362 case M68K_ADD: add_rrdisp(code, src, dst, disp, size); break;
1351 case M68K_ADDX: adc_rrdisp(code, src, dst, disp, size); break; 1363 case M68K_ADDX: adc_rrdisp(code, src, dst, disp, size); break;
1352 case M68K_AND: and_rrdisp(code, src, dst, disp, size); break; 1364 case M68K_AND: and_rrdisp(code, src, dst, disp, size); break;
1365 case M68K_BTST: bt_rrdisp(code, src, dst, disp, size); break;
1366 case M68K_BSET: bts_rrdisp(code, src, dst, disp, size); break;
1367 case M68K_BCLR: btr_rrdisp(code, src, dst, disp, size); break;
1368 case M68K_BCHG: btc_rrdisp(code, src, dst, disp, size); break;
1353 case M68K_EOR: xor_rrdisp(code, src, dst, disp, size); break; 1369 case M68K_EOR: xor_rrdisp(code, src, dst, disp, size); break;
1354 case M68K_OR: or_rrdisp(code, src, dst, disp, size); break; 1370 case M68K_OR: or_rrdisp(code, src, dst, disp, size); break;
1355 case M68K_SUB: sub_rrdisp(code, src, dst, disp, size); break; 1371 case M68K_SUB: sub_rrdisp(code, src, dst, disp, size); break;
1356 case M68K_SUBX: sbb_rrdisp(code, src, dst, disp, size); break; 1372 case M68K_SUBX: sbb_rrdisp(code, src, dst, disp, size); break;
1357 } 1373 }
1480 uint8_t dst_reg; 1496 uint8_t dst_reg;
1481 code_info *code = &opts->gen.code; 1497 code_info *code = &opts->gen.code;
1482 check_cycles_int(&opts->gen, inst->address); 1498 check_cycles_int(&opts->gen, inst->address);
1483 if (inst->op == M68K_MOVE) { 1499 if (inst->op == M68K_MOVE) {
1484 return translate_m68k_move(opts, inst); 1500 return translate_m68k_move(opts, inst);
1485 } else if(inst->op == M68K_LEA) { 1501 } else if(inst->op == M68K_LEA || inst->op == M68K_PEA) {
1486 return translate_m68k_lea(opts, inst); 1502 return translate_m68k_lea_pea(opts, inst);
1487 } else if(inst->op == M68K_PEA) {
1488 return translate_m68k_pea(opts, inst);
1489 } else if(inst->op == M68K_BSR) { 1503 } else if(inst->op == M68K_BSR) {
1490 return translate_m68k_bsr(opts, inst); 1504 return translate_m68k_bsr(opts, inst);
1491 } else if(inst->op == M68K_BCC) { 1505 } else if(inst->op == M68K_BCC) {
1492 return translate_m68k_bcc(opts, inst); 1506 return translate_m68k_bcc(opts, inst);
1493 } else if(inst->op == M68K_JMP) { 1507 } else if(inst->op == M68K_JMP) {
1635 ); 1649 );
1636 if (src_op.mode == MODE_IMMED) { 1650 if (src_op.mode == MODE_IMMED) {
1637 if (inst->extra.size == OPSIZE_BYTE) { 1651 if (inst->extra.size == OPSIZE_BYTE) {
1638 src_op.disp &= 0x7; 1652 src_op.disp &= 0x7;
1639 } 1653 }
1640 if (inst->op == M68K_BTST) { 1654 if (dst_op.mode == MODE_REG_DIRECT) {
1641 if (dst_op.mode == MODE_REG_DIRECT) { 1655 op_ir(code, inst, src_op.disp, dst_op.base, inst->extra.size);
1642 bt_ir(code, src_op.disp, dst_op.base, inst->extra.size); 1656 } else {
1643 } else { 1657 op_irdisp(code, inst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
1644 bt_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
1645 }
1646 } else if (inst->op == M68K_BSET) {
1647 if (dst_op.mode == MODE_REG_DIRECT) {
1648 bts_ir(code, src_op.disp, dst_op.base, inst->extra.size);
1649 } else {
1650 bts_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
1651 }
1652 } else if (inst->op == M68K_BCLR) {
1653 if (dst_op.mode == MODE_REG_DIRECT) {
1654 btr_ir(code, src_op.disp, dst_op.base, inst->extra.size);
1655 } else {
1656 btr_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
1657 }
1658 } else {
1659 if (dst_op.mode == MODE_REG_DIRECT) {
1660 btc_ir(code, src_op.disp, dst_op.base, inst->extra.size);
1661 } else {
1662 btc_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
1663 }
1664 } 1658 }
1665 } else { 1659 } else {
1666 if (src_op.mode == MODE_REG_DISPLACE8 || (inst->dst.addr_mode != MODE_REG && src_op.base != opts->gen.scratch1 && src_op.base != opts->gen.scratch2)) { 1660 if (src_op.mode == MODE_REG_DISPLACE8 || (inst->dst.addr_mode != MODE_REG && src_op.base != opts->gen.scratch1 && src_op.base != opts->gen.scratch2)) {
1667 if (dst_op.base == opts->gen.scratch1) { 1661 if (dst_op.base == opts->gen.scratch1) {
1668 push_r(code, opts->gen.scratch2); 1662 push_r(code, opts->gen.scratch2);
1701 //x86-64 doesn't support 8-bit bit operations 1695 //x86-64 doesn't support 8-bit bit operations
1702 //so we fake it by forcing the bit number to be modulo 8 1696 //so we fake it by forcing the bit number to be modulo 8
1703 and_ir(code, 7, src_op.base, SZ_D); 1697 and_ir(code, 7, src_op.base, SZ_D);
1704 size = SZ_D; 1698 size = SZ_D;
1705 } 1699 }
1706 if (inst->op == M68K_BTST) { 1700 if (dst_op.mode == MODE_REG_DIRECT) {
1707 if (dst_op.mode == MODE_REG_DIRECT) { 1701 op_rr(code, inst, src_op.base, dst_op.base, size);
1708 bt_rr(code, src_op.base, dst_op.base, size); 1702 } else {
1709 } else { 1703 op_rrdisp(code, inst, src_op.base, dst_op.base, dst_op.disp, size);
1710 bt_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size);
1711 }
1712 } else if (inst->op == M68K_BSET) {
1713 if (dst_op.mode == MODE_REG_DIRECT) {
1714 bts_rr(code, src_op.base, dst_op.base, size);
1715 } else {
1716 bts_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size);
1717 }
1718 } else if (inst->op == M68K_BCLR) {
1719 if (dst_op.mode == MODE_REG_DIRECT) {
1720 btr_rr(code, src_op.base, dst_op.base, size);
1721 } else {
1722 btr_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size);
1723 }
1724 } else {
1725 if (dst_op.mode == MODE_REG_DIRECT) {
1726 btc_rr(code, src_op.base, dst_op.base, size);
1727 } else {
1728 btc_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size);
1729 }
1730 } 1704 }
1731 if (src_op.base == opts->gen.scratch2) { 1705 if (src_op.base == opts->gen.scratch2) {
1732 pop_r(code, opts->gen.scratch2); 1706 pop_r(code, opts->gen.scratch2);
1733 } 1707 }
1734 } 1708 }