Mercurial > repos > blastem
comparison vdp.c @ 678:a7971650c04e
Adjusted h40_hsync_cycles so that lines actually take 3420 mclks. Fixed vdp_cycles_next_line to take h40_sync_cycles into account
author | Michael Pavone <pavone@retrodev.com> |
---|---|
date | Sun, 04 Jan 2015 12:24:34 -0800 |
parents | 5d58dcd94733 |
children | 4996369f1463 |
comparison
equal
deleted
inserted
replaced
677:687c1dd3bcb9 | 678:a7971650c04e |
---|---|
1418 } | 1418 } |
1419 } | 1419 } |
1420 } | 1420 } |
1421 } | 1421 } |
1422 | 1422 |
1423 uint32_t h40_hsync_cycles[] = {19, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 18, 20, 20, 20, 19}; | 1423 uint32_t const h40_hsync_cycles[] = {19, 20, 20, 20, 19, 20, 20, 20, 19, 20, 20, 20, 19, 20, 20, 20, 19}; |
1424 | 1424 |
1425 void vdp_run_context(vdp_context * context, uint32_t target_cycles) | 1425 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
1426 { | 1426 { |
1427 while(context->cycles < target_cycles) | 1427 while(context->cycles < target_cycles) |
1428 { | 1428 { |
1825 if (context->regs[REG_MODE_4] & BIT_H40) { | 1825 if (context->regs[REG_MODE_4] & BIT_H40) { |
1826 if (context->hslot < LINE_CHANGE_H40) { | 1826 if (context->hslot < LINE_CHANGE_H40) { |
1827 return (HBLANK_START_H40 - context->hslot) * MCLKS_SLOT_H40; | 1827 return (HBLANK_START_H40 - context->hslot) * MCLKS_SLOT_H40; |
1828 } else if (context->hslot < 183) { | 1828 } else if (context->hslot < 183) { |
1829 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H40) * MCLKS_SLOT_H40; | 1829 return MCLKS_LINE - (context->hslot - LINE_CHANGE_H40) * MCLKS_SLOT_H40; |
1830 } else if (context->hslot < HSYNC_END_H40){ | |
1831 uint32_t before_hsync = context->hslot < HSYNC_SLOT_H40 ? (HSYNC_SLOT_H40 - context->hslot) * MCLKS_SLOT_H40 : 0; | |
1832 uint32_t hsync = 0; | |
1833 for (int i = context->hslot <= HSYNC_SLOT_H40 ? 0 : context->hslot - HSYNC_SLOT_H40; i < sizeof(h40_hsync_cycles)/sizeof(uint32_t); i++) | |
1834 { | |
1835 hsync += h40_hsync_cycles[i]; | |
1836 } | |
1837 uint32_t after_hsync = (256- HSYNC_END_H40 + LINE_CHANGE_H40) * MCLKS_SLOT_H40; | |
1838 return before_hsync + hsync + after_hsync; | |
1830 } else { | 1839 } else { |
1831 return (256-context->hslot + LINE_CHANGE_H40) * MCLKS_SLOT_H40; | 1840 return (256-context->hslot + LINE_CHANGE_H40) * MCLKS_SLOT_H40; |
1832 } | 1841 } |
1833 } else { | 1842 } else { |
1834 if (context->hslot < LINE_CHANGE_H32) { | 1843 if (context->hslot < LINE_CHANGE_H32) { |