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comparison vdp.c @ 1983:a7b753e260a2 mame_interp

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Merge from default
author Michael Pavone <pavone@retrodev.com>
date Sat, 09 May 2020 23:39:44 -0700
parents 80920c21bb52
children 6b9871d3d70d
comparison
equal deleted inserted replaced
1937:cafde1255ad3 1983:a7b753e260a2
7 #include "blastem.h" 7 #include "blastem.h"
8 #include <stdlib.h> 8 #include <stdlib.h>
9 #include <string.h> 9 #include <string.h>
10 #include "render.h" 10 #include "render.h"
11 #include "util.h" 11 #include "util.h"
12 #include "event_log.h"
12 13
13 #define NTSC_INACTIVE_START 224 14 #define NTSC_INACTIVE_START 224
14 #define PAL_INACTIVE_START 240 15 #define PAL_INACTIVE_START 240
15 #define MODE4_INACTIVE_START 192 16 #define MODE4_INACTIVE_START 192
16 #define BUF_BIT_PRIORITY 0x40 17 #define BUF_BIT_PRIORITY 0x40
906 if (context->fifo_read >= 0 && start->cycle <= context->cycles) { 907 if (context->fifo_read >= 0 && start->cycle <= context->cycles) {
907 switch (start->cd & 0xF) 908 switch (start->cd & 0xF)
908 { 909 {
909 case VRAM_WRITE: 910 case VRAM_WRITE:
910 if ((context->regs[REG_MODE_2] & (BIT_128K_VRAM|BIT_MODE_5)) == (BIT_128K_VRAM|BIT_MODE_5)) { 911 if ((context->regs[REG_MODE_2] & (BIT_128K_VRAM|BIT_MODE_5)) == (BIT_128K_VRAM|BIT_MODE_5)) {
912 event_vram_word(context->cycles, start->address, start->value);
911 vdp_check_update_sat(context, start->address, start->value); 913 vdp_check_update_sat(context, start->address, start->value);
912 write_vram_word(context, start->address, start->value); 914 write_vram_word(context, start->address, start->value);
913 } else { 915 } else {
914 uint8_t byte = start->partial == 1 ? start->value >> 8 : start->value; 916 uint8_t byte = start->partial == 1 ? start->value >> 8 : start->value;
915 vdp_check_update_sat_byte(context, start->address ^ 1, byte); 917 uint32_t address = start->address ^ 1;
916 write_vram_byte(context, start->address ^ 1, byte); 918 event_vram_byte(context->cycles, start->address, byte, context->regs[REG_AUTOINC]);
919 vdp_check_update_sat_byte(context, address, byte);
920 write_vram_byte(context, address, byte);
917 if (!start->partial) { 921 if (!start->partial) {
918 start->address = start->address ^ 1; 922 start->address = address;
919 start->partial = 1; 923 start->partial = 1;
920 //skip auto-increment and removal of entry from fifo 924 //skip auto-increment and removal of entry from fifo
921 return; 925 return;
922 } 926 }
923 } 927 }
924 break; 928 break;
925 case CRAM_WRITE: { 929 case CRAM_WRITE: {
926 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); 930 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1));
931 uint16_t val;
927 if (start->partial == 3) { 932 if (start->partial == 3) {
928 uint16_t val;
929 if ((start->address & 1) && (context->regs[REG_MODE_2] & BIT_MODE_5)) { 933 if ((start->address & 1) && (context->regs[REG_MODE_2] & BIT_MODE_5)) {
930 val = (context->cram[start->address >> 1 & (CRAM_SIZE-1)] & 0xFF) | start->value << 8; 934 val = (context->cram[start->address >> 1 & (CRAM_SIZE-1)] & 0xFF) | start->value << 8;
931 } else { 935 } else {
932 uint16_t address = (context->regs[REG_MODE_2] & BIT_MODE_5) ? start->address >> 1 & (CRAM_SIZE-1) : start->address & 0x1F; 936 uint16_t address = (context->regs[REG_MODE_2] & BIT_MODE_5) ? start->address >> 1 & (CRAM_SIZE-1) : start->address & 0x1F;
933 val = (context->cram[address] & 0xFF00) | start->value; 937 val = (context->cram[address] & 0xFF00) | start->value;
934 } 938 }
935 write_cram(context, start->address, val);
936 } else { 939 } else {
937 write_cram(context, start->address, start->partial ? context->fifo[context->fifo_write].value : start->value); 940 val = start->partial ? context->fifo[context->fifo_write].value : start->value;
938 } 941 }
942 uint8_t buffer[3] = {start->address & 127, val >> 8, val};
943 event_log(EVENT_VDP_INTRAM, context->cycles, sizeof(buffer), buffer);
944 write_cram(context, start->address, val);
939 break; 945 break;
940 } 946 }
941 case VSRAM_WRITE: 947 case VSRAM_WRITE:
942 if (((start->address/2) & 63) < context->vsram_size) { 948 if (((start->address/2) & 63) < context->vsram_size) {
943 //printf("VSRAM Write: %X to %X @ frame: %d, vcounter: %d, hslot: %d, cycle: %d\n", start->value, start->address, context->frame, context->vcounter, context->hslot, context->cycles); 949 //printf("VSRAM Write: %X to %X @ frame: %d, vcounter: %d, hslot: %d, cycle: %d\n", start->value, start->address, context->frame, context->vcounter, context->hslot, context->cycles);
950 context->vsram[(start->address/2) & 63] |= start->value; 956 context->vsram[(start->address/2) & 63] |= start->value;
951 } 957 }
952 } else { 958 } else {
953 context->vsram[(start->address/2) & 63] = start->partial ? context->fifo[context->fifo_write].value : start->value; 959 context->vsram[(start->address/2) & 63] = start->partial ? context->fifo[context->fifo_write].value : start->value;
954 } 960 }
961 uint8_t buffer[3] = {((start->address/2) & 63) + 128, context->vsram[(start->address/2) & 63] >> 8, context->vsram[(start->address/2) & 63]};
962 event_log(EVENT_VDP_INTRAM, context->cycles, sizeof(buffer), buffer);
955 } 963 }
956 964
957 break; 965 break;
958 } 966 }
959 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); 967 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1);
3758 value &= 0x3F; 3766 value &= 0x3F;
3759 } 3767 }
3760 /*if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) { 3768 /*if (reg == REG_MODE_4 && ((value ^ context->regs[reg]) & BIT_H40)) {
3761 printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame); 3769 printf("Mode changed from H%d to H%d @ %d, frame: %d\n", context->regs[reg] & BIT_H40 ? 40 : 32, value & BIT_H40 ? 40 : 32, context->cycles, context->frame);
3762 }*/ 3770 }*/
3771 uint8_t buffer[2] = {reg, value};
3772 event_log(EVENT_VDP_REG, context->cycles, sizeof(buffer), buffer);
3763 context->regs[reg] = value; 3773 context->regs[reg] = value;
3764 if (reg == REG_MODE_4) { 3774 if (reg == REG_MODE_4) {
3765 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); 3775 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES);
3766 if (!context->double_res) { 3776 if (!context->double_res) {
3767 context->flags2 &= ~FLAG2_EVEN_FIELD; 3777 context->flags2 &= ~FLAG2_EVEN_FIELD;
4549 context->debug_modes[i]++; 4559 context->debug_modes[i]++;
4550 return; 4560 return;
4551 } 4561 }
4552 } 4562 }
4553 } 4563 }
4564
4565 void vdp_replay_event(vdp_context *context, uint8_t event, event_reader *reader)
4566 {
4567 uint32_t address;
4568 deserialize_buffer *buffer = &reader->buffer;
4569 switch (event)
4570 {
4571 case EVENT_VRAM_BYTE:
4572 reader_ensure_data(reader, 3);
4573 address = load_int16(buffer);
4574 break;
4575 case EVENT_VRAM_BYTE_DELTA:
4576 reader_ensure_data(reader, 2);
4577 address = reader->last_byte_address + load_int8(buffer);
4578 break;
4579 case EVENT_VRAM_BYTE_ONE:
4580 reader_ensure_data(reader, 1);
4581 address = reader->last_byte_address + 1;
4582 break;
4583 case EVENT_VRAM_BYTE_AUTO:
4584 reader_ensure_data(reader, 1);
4585 address = reader->last_byte_address + context->regs[REG_AUTOINC];
4586 break;
4587 case EVENT_VRAM_WORD:
4588 reader_ensure_data(reader, 4);
4589 address = load_int8(buffer) << 16;
4590 address |= load_int16(buffer);
4591 break;
4592 case EVENT_VRAM_WORD_DELTA:
4593 reader_ensure_data(reader, 3);
4594 address = reader->last_word_address + load_int8(buffer);
4595 break;
4596 case EVENT_VDP_REG:
4597 case EVENT_VDP_INTRAM:
4598 reader_ensure_data(reader, event == EVENT_VDP_REG ? 2 : 3);
4599 address = load_int8(buffer);
4600 break;
4601 }
4602
4603 switch (event)
4604 {
4605 case EVENT_VDP_REG: {
4606 uint8_t value = load_int8(buffer);
4607 context->regs[address] = value;
4608 if (address == REG_MODE_4) {
4609 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES);
4610 if (!context->double_res) {
4611 context->flags2 &= ~FLAG2_EVEN_FIELD;
4612 }
4613 }
4614 if (address == REG_MODE_1 || address == REG_MODE_2 || address == REG_MODE_4) {
4615 update_video_params(context);
4616 }
4617 break;
4618 }
4619 case EVENT_VRAM_BYTE:
4620 case EVENT_VRAM_BYTE_DELTA:
4621 case EVENT_VRAM_BYTE_ONE:
4622 case EVENT_VRAM_BYTE_AUTO: {
4623 uint8_t byte = load_int8(buffer);
4624 reader->last_byte_address = address;
4625 vdp_check_update_sat_byte(context, address ^ 1, byte);
4626 write_vram_byte(context, address ^ 1, byte);
4627 break;
4628 }
4629 case EVENT_VRAM_WORD:
4630 case EVENT_VRAM_WORD_DELTA: {
4631 uint16_t value = load_int16(buffer);
4632 reader->last_word_address = address;
4633 vdp_check_update_sat(context, address, value);
4634 write_vram_word(context, address, value);
4635 break;
4636 }
4637 case EVENT_VDP_INTRAM:
4638 if (address < 128) {
4639 write_cram(context, address, load_int16(buffer));
4640 } else {
4641 context->vsram[address&63] = load_int16(buffer);
4642 }
4643 break;
4644 }
4645 }