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comparison cpu_dsl.py @ 1722:ac809d044cab

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Implemented the rest of the rotate instructions in new Z80 core
author Michael Pavone <pavone@retrodev.com>
date Thu, 31 Jan 2019 23:03:51 -0800
parents 0e5df2bc0f9f
children b757ebc59851
comparison
equal deleted inserted replaced
1721:0e5df2bc0f9f 1722:ac809d044cab
324 myRes = lastDst 324 myRes = lastDst
325 if calc == 'sign': 325 if calc == 'sign':
326 resultBit = prog.paramSize(prog.lastDst) - 1 326 resultBit = prog.paramSize(prog.lastDst) - 1
327 elif calc == 'carry': 327 elif calc == 'carry':
328 resultBit = prog.paramSize(prog.lastDst) 328 resultBit = prog.paramSize(prog.lastDst)
329 if prog.lastOp.op == 'ror':
330 resultBit -= 1
329 elif calc == 'half': 331 elif calc == 'half':
330 resultBit = prog.paramSize(prog.lastDst) - 4 332 resultBit = prog.paramSize(prog.lastDst) - 4
331 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst) 333 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst)
332 elif calc == 'overflow': 334 elif calc == 'overflow':
333 resultBit = prog.paramSize(prog.lastDst) - 1 335 resultBit = prog.paramSize(prog.lastDst) - 1
576 return decl + '\n\t{dst} = {a} << {b} | {a} >> ({size} + 1 - {b}) | ({check} ? 1 : 0) << ({b} - 1);'.format(dst = dst, 578 return decl + '\n\t{dst} = {a} << {b} | {a} >> ({size} + 1 - {b}) | ({check} ? 1 : 0) << ({b} - 1);'.format(dst = dst,
577 a = params[0], b = params[1], size=size, check=carryCheck 579 a = params[0], b = params[1], size=size, check=carryCheck
578 ) 580 )
579 581
580 def _rorCImpl(prog, params, rawParams, flagUpdates): 582 def _rorCImpl(prog, params, rawParams, flagUpdates):
581 needsCarry = False
582 if flagUpdates:
583 for flag in flagUpdates:
584 calc = prog.flags.flagCalc[flag]
585 if calc == 'carry':
586 needsCarry = True
587 decl = ''
588 size = prog.paramSize(rawParams[2]) 583 size = prog.paramSize(rawParams[2])
589 if needsCarry: 584 return '\n\t{dst} = {a} >> {b} | {a} << ({size} - {b});'.format(dst = params[2],
590 decl,name = prog.getTemp(size)
591 dst = prog.carryFlowDst = name
592 else:
593 dst = params[2]
594 return decl + '\n\t{dst} = {a} >> {b} | {a} << ({size} - {b});'.format(dst = dst,
595 a = params[0], b = params[1], size=size 585 a = params[0], b = params[1], size=size
596 ) 586 )
597 587
598 def _rrcCImpl(prog, params, rawParams, flagUpdates): 588 def _rrcCImpl(prog, params, rawParams, flagUpdates):
599 needsCarry = False 589 needsCarry = False