Mercurial > repos > blastem
comparison cpu_dsl.py @ 2502:ad50530a7c27
Partially functional asr/asl implementations in new 68K core
author | Michael Pavone <pavone@retrodev.com> |
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date | Tue, 16 Jul 2024 20:21:08 -0700 |
parents | d44fe974fb85 |
children | 595719fe69f2 |
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2501:6cd5a1d76e34 | 2502:ad50530a7c27 |
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500 elif calc == 'carry': | 500 elif calc == 'carry': |
501 if prog.lastOp.op in ('asr', 'lsr'): | 501 if prog.lastOp.op in ('asr', 'lsr'): |
502 if type(prog.lastB) is int: | 502 if type(prog.lastB) is int: |
503 resultBit = prog.lastB - 1 | 503 resultBit = prog.lastB - 1 |
504 else: | 504 else: |
505 #FIXME!!!!! | 505 resultBit = f'({prog.lastB} - 1)' |
506 resultBit = 0 | |
507 myRes = prog.lastA | 506 myRes = prog.lastA |
508 elif prog.lastOp.op == 'neg': | 507 elif prog.lastOp.op == 'neg': |
509 if prog.carryFlowDst: | 508 if prog.carryFlowDst: |
510 realSize = prog.getLastSize() | 509 realSize = prog.getLastSize() |
511 if realSize != prog.paramSize(prog.carryFlowDst): | 510 if realSize != prog.paramSize(prog.carryFlowDst): |
552 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift | 551 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift |
553 )) | 552 )) |
554 else: | 553 else: |
555 reg = prog.resolveParam(storage, None, {}) | 554 reg = prog.resolveParam(storage, None, {}) |
556 maxBit = prog.paramSize(storage) - 1 | 555 maxBit = prog.paramSize(storage) - 1 |
557 if resultBit > maxBit: | 556 if type(resultBit) is int: |
558 output.append('\n\t{reg} = {res} >> {shift} & {mask}U;'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = 1 << maxBit)) | 557 mask = f'{1 << resultBit}U' |
559 else: | 558 else: |
560 output.append('\n\t{reg} = {res} & {mask}U;'.format(reg=reg, res=myRes, mask = 1 << resultBit)) | 559 mask = f'(1 << {resultBit})' |
560 if not type(resultBit) is int: | |
561 output.append(f'\n\t{reg} = !!({myRes} & {mask});') | |
562 elif resultBit > maxBit: | |
563 mask = f'{1 << maxBit}U' | |
564 output.append('\n\t{reg} = {res} >> {shift} & {mask};'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = mask)) | |
565 else: | |
566 output.append('\n\t{reg} = {res} & {mask};'.format(reg=reg, res=myRes, mask = mask)) | |
561 elif calc == 'zero': | 567 elif calc == 'zero': |
562 if prog.carryFlowDst: | 568 if prog.carryFlowDst: |
563 realSize = prog.getLastSize() | 569 realSize = prog.getLastSize() |
564 if realSize != prog.paramSize(prog.carryFlowDst): | 570 if realSize != prog.paramSize(prog.carryFlowDst): |
565 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1) | 571 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1) |
692 for flag in flagUpdates: | 698 for flag in flagUpdates: |
693 calc = prog.flags.flagCalc[flag] | 699 calc = prog.flags.flagCalc[flag] |
694 if calc == 'carry': | 700 if calc == 'carry': |
695 needsCarry = True | 701 needsCarry = True |
696 decl = '' | 702 decl = '' |
697 size = prog.paramSize(rawParams[2]) | 703 needsSizeAdjust = False |
704 destSize = prog.paramSize(rawParams[2]) | |
705 if len(params) > 3: | |
706 size = params[3] | |
707 if size == 0: | |
708 size = 8 | |
709 elif size == 1: | |
710 size = 16 | |
711 else: | |
712 size = 32 | |
713 prog.lastSize = size | |
714 if destSize > size: | |
715 needsSizeAdjust = True | |
716 prog.sizeAdjust = size | |
717 else: | |
718 size = destSize | |
719 mask = 1 << (size - 1) | |
698 if needsCarry: | 720 if needsCarry: |
699 decl,name = prog.getTemp(size * 2) | 721 decl,name = prog.getTemp(size) |
700 dst = prog.carryFlowDst = name | 722 dst = prog.carryFlowDst = name |
701 prog.lastA = params[0] | 723 prog.lastA = params[0] |
724 prog.lastB = params[1] | |
725 if needsSizeAdjust: | |
726 sizeMask = (1 << size) - 1 | |
727 return decl + '\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);'.format( | |
728 name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask) | |
729 elif needsSizeAdjust: | |
730 decl,name = prog.getTemp(size) | |
731 sizeMask = (1 << size) - 1 | |
732 return decl + ('\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);' + | |
733 '\n\t{dst} = ({dst} & ~{sizeMask}) | {name};').format( | |
734 name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask) | |
702 else: | 735 else: |
703 dst = params[2] | 736 dst = params[2] |
704 mask = 1 << (size - 1) | 737 |
705 return decl + '\n\t{dst} = ({a} >> {b}) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format( | 738 return decl + '\n\t{dst} = ({a} >> {b}) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format( |
706 a = params[0], b = params[1], dst = dst, mask = mask, size=size) | 739 a = params[0], b = params[1], dst = dst, mask = mask, size=size) |
707 | 740 |
708 def _sext(size, src): | 741 def _sext(size, src): |
709 if size == 16: | 742 if size == 16: |