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Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
author Mike Pavone <pavone@retrodev.com>
date Wed, 19 Dec 2012 22:15:16 -0800
parents a6dd5b7a971b
children 108e587165c0
comparison
equal deleted inserted replaced
64:2b1a65f4b85d 65:aef6302770c2
193 case VRAM_WRITE: 193 case VRAM_WRITE:
194 if (start->partial) { 194 if (start->partial) {
195 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1); 195 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1);
196 context->vdpmem[context->address ^ 1] = start->value; 196 context->vdpmem[context->address ^ 1] = start->value;
197 } else { 197 } else {
198 //printf("VRAM Write: %X to %X\n", start->value >> 8, context->address); 198 //printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address);
199 context->vdpmem[context->address] = start->value >> 8; 199 context->vdpmem[context->address] = start->value >> 8;
200 start->partial = 1; 200 start->partial = 1;
201 //skip auto-increment and removal of entry from fifo 201 //skip auto-increment and removal of entry from fifo
202 return; 202 return;
203 } 203 }
918 918
919 void vdp_data_port_write(vdp_context * context, uint16_t value) 919 void vdp_data_port_write(vdp_context * context, uint16_t value)
920 { 920 {
921 //printf("data port write: %X\n", value); 921 //printf("data port write: %X\n", value);
922 context->flags &= ~FLAG_PENDING; 922 context->flags &= ~FLAG_PENDING;
923 /*if (context->fifo_cur == context->fifo_end) { 923 if (context->fifo_cur == context->fifo_end) {
924 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); 924 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
925 }*/ 925 }
926 while (context->fifo_cur == context->fifo_end) { 926 while (context->fifo_cur == context->fifo_end) {
927 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); 927 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
928 } 928 }
929 context->fifo_cur->cycle = context->cycles; 929 context->fifo_cur->cycle = context->cycles;
930 context->fifo_cur->value = value; 930 context->fifo_cur->value = value;
979 } 979 }
980 context->address += context->regs[REG_AUTOINC]; 980 context->address += context->regs[REG_AUTOINC];
981 return value; 981 return value;
982 } 982 }
983 983
984 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction)
985 {
986 context->cycles -= deduction;
987 for(fifo_entry * start = (context->fifo_end - FIFO_SIZE); start < context->fifo_cur; start++) {
988 if (start->cycle >= deduction) {
989 start->cycle -= deduction;
990 } else {
991 start->cycle = 0;
992 }
993 }
994 }
995
984 #define GST_VDP_REGS 0xFA 996 #define GST_VDP_REGS 0xFA
985 #define GST_VDP_MEM 0x12478 997 #define GST_VDP_MEM 0x12478
986 998
987 void vdp_load_savestate(vdp_context * context, FILE * state_file) 999 void vdp_load_savestate(vdp_context * context, FILE * state_file)
988 { 1000 {