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comparison m68k.cpu @ 2454:b1e8e7554f2f

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Implement bit instructions in new CPU core
author Michael Pavone <pavone@retrodev.com>
date Mon, 19 Feb 2024 22:52:21 -0800
parents 7d7525769ce2
children 72d0eac49507
comparison
equal deleted inserted replaced
2453:7d7525769ce2 2454:b1e8e7554f2f
1387 end 1387 end
1388 cmp src aregs.D 1388 cmp src aregs.D
1389 update_flags NZVC 1389 update_flags NZVC
1390 m68k_prefetch 1390 m68k_prefetch
1391 1391
1392 0000100000MMMRRR btsti
1393 invalid M 1
1394 invalid M 7 R 5
1395 invalid M 7 R 6
1396 invalid M 7 R 7
1397
1398 local tmp 32
1399 m68k_prefetch
1400 if M
1401 tmp = scratch1 & 7
1402 meta size 0
1403 else
1404 cycles 2
1405 tmp = scratch1 & 31
1406 meta size 2
1407 end
1408 tmp = 1 << tmp
1409 m68k_fetch_src_ea M R size
1410 tmp &= src
1411 update_flags Z
1412 m68k_prefetch
1413
1414 0000100001MMMRRR bchgi
1415 invalid M 1
1416 invalid M 7 R 2
1417 invalid M 7 R 3
1418 invalid M 7 R 4
1419 invalid M 7 R 5
1420 invalid M 7 R 6
1421 invalid M 7 R 7
1422
1423 local tmp 32
1424 local tmp2 32
1425 m68k_prefetch
1426 if M
1427 tmp = scratch1 & 7
1428 meta size 0
1429 else
1430 tmp = scratch1 & 31
1431 meta size 2
1432 if tmp >=U 16
1433 cycles 4
1434 else
1435 cycles 2
1436 end
1437 end
1438 tmp = 1 << tmp
1439 m68k_fetch_dst_ea M R size
1440 tmp2 = tmp & dst
1441 update_flags Z
1442 dst ^= tmp
1443 m68k_save_dst size
1444 m68k_prefetch
1445
1446 0000100010MMMRRR bclri
1447 invalid M 1
1448 invalid M 7 R 2
1449 invalid M 7 R 3
1450 invalid M 7 R 4
1451 invalid M 7 R 5
1452 invalid M 7 R 6
1453 invalid M 7 R 7
1454
1455 local tmp 32
1456 local tmp2 32
1457 m68k_prefetch
1458 if M
1459 tmp = scratch1 & 7
1460 meta size 0
1461 else
1462 tmp = scratch1 & 31
1463 meta size 2
1464 if tmp >=U 16
1465 cycles 6
1466 else
1467 cycles 4
1468 end
1469 end
1470 tmp = 1 << tmp
1471 m68k_fetch_dst_ea M R size
1472 tmp2 = tmp & dst
1473 update_flags Z
1474 tmp = ~tmp
1475 dst &= tmp
1476 m68k_save_dst size
1477 m68k_prefetch
1478
1479 0000100011MMMRRR bseti
1480 invalid M 1
1481 invalid M 7 R 2
1482 invalid M 7 R 3
1483 invalid M 7 R 4
1484 invalid M 7 R 5
1485 invalid M 7 R 6
1486 invalid M 7 R 7
1487
1488 local tmp 32
1489 local tmp2 32
1490 m68k_prefetch
1491 if M
1492 tmp = scratch1 & 7
1493 meta size 0
1494 else
1495 tmp = scratch1 & 31
1496 meta size 2
1497 if tmp >=U 16
1498 cycles 4
1499 else
1500 cycles 2
1501 end
1502 end
1503 tmp = 1 << tmp
1504 m68k_fetch_dst_ea M R size
1505 tmp2 = tmp & dst
1506 update_flags Z
1507 dst |= tmp
1508 m68k_save_dst size
1509 m68k_prefetch
1510
1511 0000SSS100MMMRRR btst_dn
1512 invalid M 1
1513 invalid M 7 R 5
1514 invalid M 7 R 6
1515 invalid M 7 R 7
1516
1517 local tmp 32
1518 if M
1519 tmp = dregs.S & 7
1520 meta size 0
1521 else
1522 tmp = dregs.S & 31
1523 meta size 2
1524 cycles 2
1525 end
1526 tmp = 1 << tmp
1527 m68k_fetch_src_ea M R size
1528 tmp &= src
1529 update_flags Z
1530 m68k_prefetch
1531
1532 0000SSS101MMMRRR bchg_dn
1533 invalid M 1
1534 invalid M 7 R 2
1535 invalid M 7 R 3
1536 invalid M 7 R 4
1537 invalid M 7 R 5
1538 invalid M 7 R 6
1539 invalid M 7 R 7
1540
1541 local tmp 32
1542 local tmp2 32
1543 if M
1544 tmp = dregs.S & 7
1545 meta size 0
1546 else
1547 tmp = dregs.S & 31
1548 meta size 2
1549 if tmp >=U 16
1550 cycles 4
1551 else
1552 cycles 2
1553 end
1554 end
1555 tmp = 1 << tmp
1556 m68k_fetch_dst_ea M R size
1557 tmp2 = tmp & dst
1558 update_flags Z
1559 dst ^= tmp
1560 m68k_save_dst size
1561 m68k_prefetch
1562
1563 0000SSS110MMMRRR bclr_dn
1564 invalid M 1
1565 invalid M 7 R 2
1566 invalid M 7 R 3
1567 invalid M 7 R 4
1568 invalid M 7 R 5
1569 invalid M 7 R 6
1570 invalid M 7 R 7
1571
1572 local tmp 32
1573 local tmp2 32
1574 if M
1575 tmp = dregs.S & 7
1576 meta size 0
1577 else
1578 tmp = dregs.S & 31
1579 meta size 2
1580 if tmp >=U 16
1581 cycles 6
1582 else
1583 cycles 4
1584 end
1585 end
1586 tmp = 1 << tmp
1587 m68k_fetch_dst_ea M R size
1588 tmp2 = tmp & dst
1589 update_flags Z
1590 tmp = ~tmp
1591 dst &= tmp
1592 m68k_save_dst size
1593 m68k_prefetch
1594
1595 0000SSS111MMMRRR bset_dn
1596 invalid M 1
1597 invalid M 7 R 2
1598 invalid M 7 R 3
1599 invalid M 7 R 4
1600 invalid M 7 R 5
1601 invalid M 7 R 6
1602 invalid M 7 R 7
1603
1604 local tmp 32
1605 local tmp2 32
1606 if M
1607 tmp = dregs.S & 7
1608 meta size 0
1609 else
1610 tmp = dregs.S & 31
1611 meta size 2
1612 if tmp >=U 16
1613 cycles 4
1614 else
1615 cycles 2
1616 end
1617 end
1618 tmp = 1 << tmp
1619 m68k_fetch_dst_ea M R size
1620 tmp2 = tmp & dst
1621 update_flags Z
1622 dst |= tmp
1623 m68k_save_dst size
1624 m68k_prefetch
1625
1392 0100111001110000 reset 1626 0100111001110000 reset
1393 if reset_handler 1627 if reset_handler
1394 pcall reset_handler m68k_reset_handler context 1628 pcall reset_handler m68k_reset_handler context
1395 end 1629 end
1396 cycles 128 1630 cycles 128