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comparison blastem.c @ 453:b491df8bdbc0

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Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
author Mike Pavone <pavone@retrodev.com>
date Mon, 02 Sep 2013 00:20:56 -0700
parents 608815ab4ff2
children 848a3db9d0b0
comparison
equal deleted inserted replaced
452:608815ab4ff2 453:b491df8bdbc0
219 gen->ym->current_cycle -= mclks_per_frame; 219 gen->ym->current_cycle -= mclks_per_frame;
220 gen->psg->cycles -= mclks_per_frame; 220 gen->psg->cycles -= mclks_per_frame;
221 if (gen->ym->write_cycle != CYCLE_NEVER) { 221 if (gen->ym->write_cycle != CYCLE_NEVER) {
222 gen->ym->write_cycle = gen->ym->write_cycle >= mclks_per_frame/MCLKS_PER_68K ? gen->ym->write_cycle - mclks_per_frame/MCLKS_PER_68K : 0; 222 gen->ym->write_cycle = gen->ym->write_cycle >= mclks_per_frame/MCLKS_PER_68K ? gen->ym->write_cycle - mclks_per_frame/MCLKS_PER_68K : 0;
223 } 223 }
224 printf("reached frame end | 68K Cycles: %d, MCLK Cycles: %d\n", context->current_cycle, mclks); 224 //printf("reached frame end | 68K Cycles: %d, MCLK Cycles: %d\n", context->current_cycle, mclks);
225 vdp_run_context(v_context, mclks_per_frame); 225 vdp_run_context(v_context, mclks_per_frame);
226 226
227 if (!headless) { 227 if (!headless) {
228 break_on_sync |= wait_render_frame(v_context, frame_limit); 228 break_on_sync |= wait_render_frame(v_context, frame_limit);
229 } 229 }
294 while (vdp_data_port_write(v_context, value) < 0) { 294 while (vdp_data_port_write(v_context, value) < 0) {
295 while(v_context->flags & FLAG_DMA_RUN) { 295 while(v_context->flags & FLAG_DMA_RUN) {
296 vdp_run_dma_done(v_context, mclks_per_frame); 296 vdp_run_dma_done(v_context, mclks_per_frame);
297 if (v_context->cycles >= mclks_per_frame) { 297 if (v_context->cycles >= mclks_per_frame) {
298 if (!headless) { 298 if (!headless) {
299 printf("reached frame end | 68K Cycles: %d, MCLK Cycles: %d\n", context->current_cycle, v_context->cycles); 299 //printf("reached frame end | 68K Cycles: %d, MCLK Cycles: %d\n", context->current_cycle, v_context->cycles);
300 wait_render_frame(v_context, frame_limit); 300 wait_render_frame(v_context, frame_limit);
301 } 301 }
302 vdp_adjust_cycles(v_context, mclks_per_frame); 302 vdp_adjust_cycles(v_context, mclks_per_frame);
303 genesis_context * gen = context->system; 303 genesis_context * gen = context->system;
304 io_adjust_cycles(gen->ports, v_context->cycles/MCLKS_PER_68K, mclks_per_frame/MCLKS_PER_68K); 304 io_adjust_cycles(gen->ports, v_context->cycles/MCLKS_PER_68K, mclks_per_frame/MCLKS_PER_68K);
354 } else { 354 } else {
355 printf("Illegal write to HV Counter port %X\n", vdp_port); 355 printf("Illegal write to HV Counter port %X\n", vdp_port);
356 exit(1); 356 exit(1);
357 } 357 }
358 if (v_context->cycles != before_cycle) { 358 if (v_context->cycles != before_cycle) {
359 printf("68K paused for %d cycles at cycle %d\n", v_context->cycles / MCLKS_PER_68K - context->current_cycle, context->current_cycle); 359 //printf("68K paused for %d cycles at cycle %d\n", v_context->cycles / MCLKS_PER_68K - context->current_cycle, context->current_cycle);
360 context->current_cycle = v_context->cycles / MCLKS_PER_68K; 360 context->current_cycle = v_context->cycles / MCLKS_PER_68K;
361 } 361 }
362 } else if (vdp_port < 0x18) { 362 } else if (vdp_port < 0x18) {
363 genesis_context * gen = context->system; 363 genesis_context * gen = context->system;
364 sync_sound(gen, context->current_cycle * MCLKS_PER_68K); 364 sync_sound(gen, context->current_cycle * MCLKS_PER_68K);