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comparison backend_x86.c @ 2138:b6338e18787e

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Fix some dynarec code invalidation issues
author Michael Pavone <pavone@retrodev.com>
date Sat, 19 Mar 2022 15:50:45 -0700
parents 9caebcfeac72
children f82c090c1e89
comparison
equal deleted inserted replaced
2137:3ef9456b76cf 2138:b6338e18787e
164 164
165 if (memmap[chunk].mask != opts->address_mask) { 165 if (memmap[chunk].mask != opts->address_mask) {
166 and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size); 166 and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size);
167 } 167 }
168 code_ptr after_normal = NULL; 168 code_ptr after_normal = NULL;
169 uint8_t need_addr_pop = 0;
169 if (size == SZ_B && memmap[chunk].shift != 0) { 170 if (size == SZ_B && memmap[chunk].shift != 0) {
171 if (is_write && (memmap[chunk].flags & MMAP_CODE)) {
172 push_r(code, adr_reg);
173 need_addr_pop = 1;
174 }
170 btr_ir(code, 0, adr_reg, opts->address_size); 175 btr_ir(code, 0, adr_reg, opts->address_size);
171 code_ptr normal = code->cur+1; 176 code_ptr normal = code->cur+1;
172 jcc(code, CC_NC, normal); 177 jcc(code, CC_NC, normal);
173 if (memmap[chunk].shift > 0) { 178 if (memmap[chunk].shift > 0) {
174 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size); 179 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size);
179 after_normal = code->cur + 1; 184 after_normal = code->cur + 1;
180 jmp(code, after_normal); 185 jmp(code, after_normal);
181 *normal = code->cur - (normal + 1); 186 *normal = code->cur - (normal + 1);
182 } 187 }
183 if (memmap[chunk].shift > 0) { 188 if (memmap[chunk].shift > 0) {
189 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) {
190 push_r(code, adr_reg);
191 need_addr_pop = 1;
192 }
184 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size); 193 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size);
185 } else if (memmap[chunk].shift < 0) { 194 } else if (memmap[chunk].shift < 0) {
195 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) {
196 push_r(code, adr_reg);
197 need_addr_pop = 1;
198 }
186 shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size); 199 shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size);
187 } 200 }
188 if (after_normal) { 201 if (after_normal) {
189 *after_normal = code->cur - (after_normal + 1); 202 *after_normal = code->cur - (after_normal + 1);
190 } 203 }
230 xor_ir(code, 1, adr_reg, opts->address_size); 243 xor_ir(code, 1, adr_reg, opts->address_size);
231 } 244 }
232 if (opts->address_size != SZ_D) { 245 if (opts->address_size != SZ_D) {
233 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D); 246 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D);
234 } 247 }
235 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { 248 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) {
236 push_r(code, adr_reg); 249 push_r(code, adr_reg);
250 need_addr_pop = 1;
237 } 251 }
238 add_rdispr(code, opts->context_reg, opts->mem_ptr_off + sizeof(void*) * memmap[chunk].ptr_index, adr_reg, SZ_PTR); 252 add_rdispr(code, opts->context_reg, opts->mem_ptr_off + sizeof(void*) * memmap[chunk].ptr_index, adr_reg, SZ_PTR);
239 if (is_write) { 253 if (is_write) {
240 mov_rrind(code, opts->scratch1, opts->scratch2, size); 254 mov_rrind(code, opts->scratch1, opts->scratch2, size);
241 if (memmap[chunk].flags & MMAP_CODE) {
242 pop_r(code, adr_reg);
243 }
244 } else { 255 } else {
245 mov_rindr(code, opts->scratch1, opts->scratch1, size); 256 mov_rindr(code, opts->scratch1, opts->scratch1, size);
246 } 257 }
247 } else { 258 } else {
248 uint8_t tmp_size = size; 259 uint8_t tmp_size = size;
281 push_r(code, opts->scratch2); 292 push_r(code, opts->scratch2);
282 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR); 293 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR);
283 add_rdispr(code, RSP, 0, opts->scratch2, SZ_PTR); 294 add_rdispr(code, RSP, 0, opts->scratch2, SZ_PTR);
284 mov_rrind(code, opts->scratch1, opts->scratch2, tmp_size); 295 mov_rrind(code, opts->scratch1, opts->scratch2, tmp_size);
285 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { 296 if (is_write && (memmap[chunk].flags & MMAP_CODE)) {
286 pop_r(code, opts->scratch2); 297 need_addr_pop = 1;
287 } else { 298 } else {
288 add_ir(code, sizeof(void*), RSP, SZ_PTR); 299 add_ir(code, sizeof(void*), RSP, SZ_PTR);
289 code->stack_off -= sizeof(void *); 300 code->stack_off -= sizeof(void *);
290 } 301 }
291 } else { 302 } else {
303 or_ir(code, 0xFF00, opts->scratch1, SZ_W); 314 or_ir(code, 0xFF00, opts->scratch1, SZ_W);
304 } 315 }
305 } 316 }
306 } 317 }
307 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { 318 if (is_write && (memmap[chunk].flags & MMAP_CODE)) {
319 if (need_addr_pop) {
320 pop_r(code, adr_reg);
321 }
308 mov_rr(code, opts->scratch2, opts->scratch1, opts->address_size); 322 mov_rr(code, opts->scratch2, opts->scratch1, opts->address_size);
309 shr_ir(code, opts->ram_flags_shift, opts->scratch1, opts->address_size); 323 shr_ir(code, opts->ram_flags_shift, opts->scratch1, opts->address_size);
310 bt_rrdisp(code, opts->scratch1, opts->context_reg, ram_flags_off, opts->address_size); 324 bt_rrdisp(code, opts->scratch1, opts->context_reg, ram_flags_off, opts->address_size);
311 code_ptr not_code = code->cur + 1; 325 code_ptr not_code = code->cur + 1;
312 jcc(code, CC_NC, code->cur + 2); 326 jcc(code, CC_NC, code->cur + 2);