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comparison z80_to_x86.c @ 307:b6393b89a7e4

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Complete flag behavior for Z80 BIT instruction
author Mike Pavone <pavone@retrodev.com>
date Wed, 08 May 2013 23:44:49 -0700
parents 3970006fae90
children e0e81551fd7e
comparison
equal deleted inserted replaced
306:3970006fae90 307:b6393b89a7e4
1158 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 1158 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
1159 dst = zcycles(dst, 1); 1159 dst = zcycles(dst, 1);
1160 } 1160 }
1161 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B); 1161 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B);
1162 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_Z)); 1162 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_Z));
1163 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_PV));
1164 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
1165 if (inst->immed == 7) {
1166 dst = cmp_ir(dst, 0, src_op.base, SZ_B);
1167 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
1168 } else {
1169 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B);
1170 }
1163 break; 1171 break;
1164 case Z80_SET: 1172 case Z80_SET:
1165 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; 1173 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
1166 dst = zcycles(dst, cycles); 1174 dst = zcycles(dst, cycles);
1167 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY); 1175 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY);