comparison vdp.c @ 1319:b6796d63977f

Fix some edge cases with regards to 128KB VRAM mode and the SAT cache
author Michael Pavone <pavone@retrodev.com>
date Sun, 16 Apr 2017 18:43:34 -0700
parents bfdd450e7dea
children df3d690cb2c3
comparison
equal deleted inserted replaced
1318:bfdd450e7dea 1319:b6796d63977f
755 context->flags &= ~FLAG_DMA_RUN; 755 context->flags &= ~FLAG_DMA_RUN;
756 context->cd &= 0xF; 756 context->cd &= 0xF;
757 } 757 }
758 } 758 }
759 759
760 void write_vram_word(vdp_context *context, uint32_t address, uint8_t value)
761 {
762 if (!(address & 4)) {
763 uint32_t sat_address = (context->regs[REG_SAT] & 0xFF) << 9;
764 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
765 uint16_t cache_address = address - sat_address;
766 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC);
767 context->sat_cache[cache_address] = value >> 8;
768 context->sat_cache[cache_address^1] = value;
769 }
770 }
771 address = (address & 0x3FC) | (address >> 1 & 0xFC01) | (address >> 9 & 0x2);
772 address ^= 1;
773 //TODO: Support an option to actually have 128KB of VRAM
774 context->vdpmem[address] = value;
775 }
776
760 void write_vram_byte(vdp_context *context, uint32_t address, uint8_t value) 777 void write_vram_byte(vdp_context *context, uint32_t address, uint8_t value)
761 { 778 {
762 if (context->regs[REG_MODE_2] & BIT_MODE_5) { 779 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
763 if (context->regs[REG_MODE_2] & BIT_128K_VRAM) {
764 address = (address & 0x3FC) | (address >> 1 & 0xFC01) | (address >> 9 & 0x2);
765 address ^= 1;
766 } else {
767 address &= 0xFFFF;
768 }
769 if (!(address & 4)) { 780 if (!(address & 4)) {
770 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; 781 uint32_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
771 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) { 782 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
772 uint16_t cache_address = address - sat_address; 783 uint16_t cache_address = address - sat_address;
773 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC); 784 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC);
774 context->sat_cache[cache_address] = value; 785 context->sat_cache[cache_address] = value;
775 } 786 }
776 } 787 }
788 address &= 0xFFFF;
777 } else { 789 } else {
778 address = mode4_address_map[address & 0x3FFF]; 790 address = mode4_address_map[address & 0x3FFF];
779 } 791 }
780 context->vdpmem[address] = value; 792 context->vdpmem[address] = value;
781 } 793 }
794 if (context->fifo_read >= 0 && start->cycle <= context->cycles) { 806 if (context->fifo_read >= 0 && start->cycle <= context->cycles) {
795 switch (start->cd & 0xF) 807 switch (start->cd & 0xF)
796 { 808 {
797 case VRAM_WRITE: 809 case VRAM_WRITE:
798 //TODO: Support actually having 128K VRAM as an option 810 //TODO: Support actually having 128K VRAM as an option
799 if (start->partial || (context->regs[REG_MODE_2] & BIT_128K_VRAM)) { 811 if ((context->regs[REG_MODE_2] & (BIT_128K_VRAM|BIT_MODE_5)) == (BIT_128K_VRAM|BIT_MODE_5)) {
812 write_vram_word(context, start->address, start->value);
813 } else if (start->partial) {
800 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); 814 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
801 write_vram_byte(context, start->address ^ 1, start->partial == 2 ? start->value >> 8 : start->value); 815 write_vram_byte(context, start->address ^ 1, start->partial == 2 ? start->value >> 8 : start->value);
802 } else { 816 } else {
803 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); 817 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
804 write_vram_byte(context, start->address, start->value >> 8); 818 write_vram_byte(context, start->address, start->value >> 8);