comparison cpu_dsl.py @ 1723:b757ebc59851

Implemented shift instructions in new Z80 core
author Michael Pavone <pavone@retrodev.com>
date Thu, 31 Jan 2019 23:33:36 -0800
parents ac809d044cab
children 89ee53a149ea
comparison
equal deleted inserted replaced
1722:ac809d044cab 1723:b757ebc59851
240 elif calc == 'overflow': 240 elif calc == 'overflow':
241 needsOflow = True 241 needsOflow = True
242 decl = '' 242 decl = ''
243 if needsCarry or needsOflow or needsHalf: 243 if needsCarry or needsOflow or needsHalf:
244 size = prog.paramSize(rawParams[2]) 244 size = prog.paramSize(rawParams[2])
245 if needsCarry: 245 if needsCarry and op != 'lsr':
246 size *= 2 246 size *= 2
247 decl,name = prog.getTemp(size) 247 decl,name = prog.getTemp(size)
248 dst = prog.carryFlowDst = name 248 dst = prog.carryFlowDst = name
249 prog.lastA = a 249 prog.lastA = a
250 prog.lastB = b 250 prog.lastB = b
323 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow': 323 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow':
324 myRes = lastDst 324 myRes = lastDst
325 if calc == 'sign': 325 if calc == 'sign':
326 resultBit = prog.paramSize(prog.lastDst) - 1 326 resultBit = prog.paramSize(prog.lastDst) - 1
327 elif calc == 'carry': 327 elif calc == 'carry':
328 resultBit = prog.paramSize(prog.lastDst) 328 if prog.lastOp.op in ('asr', 'lsr'):
329 if prog.lastOp.op == 'ror': 329 resultBit = 0
330 resultBit -= 1 330 myRes = prog.lastA
331 else:
332 resultBit = prog.paramSize(prog.lastDst)
333 if prog.lastOp.op == 'ror':
334 resultBit -= 1
331 elif calc == 'half': 335 elif calc == 'half':
332 resultBit = prog.paramSize(prog.lastDst) - 4 336 resultBit = prog.paramSize(prog.lastDst) - 4
333 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst) 337 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst)
334 elif calc == 'overflow': 338 elif calc == 'overflow':
335 resultBit = prog.paramSize(prog.lastDst) - 1 339 resultBit = prog.paramSize(prog.lastDst) - 1
451 if not scope.resolveLocal(tmpvar): 455 if not scope.resolveLocal(tmpvar):
452 scope.addLocal(tmpvar, size) 456 scope.addLocal(tmpvar, size)
453 prog.lastDst = rawParams[1] 457 prog.lastDst = rawParams[1]
454 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = params[0], b = params[1]) 458 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = params[0], b = params[1])
455 459
456 def _asrCImpl(prog, params, rawParams): 460 def _asrCImpl(prog, params, rawParams, flagUpdates):
457 shiftSize = prog.paramSize(rawParams[0]) 461 needsCarry = False
458 mask = 1 << (shiftSize - 1) 462 if flagUpdates:
459 return '\n\t{dst} = ({a} >> {b}) | ({a} & {mask});'.format(a = params[0], b = params[1], dst = params[2], mask = mask) 463 for flag in flagUpdates:
464 calc = prog.flags.flagCalc[flag]
465 if calc == 'carry':
466 needsCarry = True
467 decl = ''
468 size = prog.paramSize(rawParams[2])
469 if needsCarry:
470 decl,name = prog.getTemp(size * 2)
471 dst = prog.carryFlowDst = name
472 prog.lastA = params[0]
473 else:
474 dst = params[2]
475 mask = 1 << (size - 1)
476 return decl + '\n\t{dst} = ({a} >> {b}) | ({a} & {mask} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format(
477 a = params[0], b = params[1], dst = dst, mask = mask, size=size)
460 478
461 def _sext(size, src): 479 def _sext(size, src):
462 if size == 16: 480 if size == 16:
463 return src | 0xFF00 if src & 0x80 else src 481 return src | 0xFF00 if src & 0x80 else src
464 else: 482 else: