Mercurial > repos > blastem
comparison blastem.c @ 508:b976c6d6e5fb
Initial attempt at emulating extended bank area access delays when 68K bus is busy with VDP stuff. Also emulate the extra delay on the second access of a word-wide read to the bank area. Needs work as it seems to break stuff.
author | Michael Pavone <pavone@retrodev.com> |
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date | Mon, 03 Feb 2014 09:18:10 -0800 |
parents | b7b7a1cab44a |
children | a277de8c1a18 |
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507:cc6030bd04c6 | 508:b976c6d6e5fb |
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310 } | 310 } |
311 vdp_port &= 0x1F; | 311 vdp_port &= 0x1F; |
312 //printf("vdp_port write: %X, value: %X, cycle: %d\n", vdp_port, value, context->current_cycle); | 312 //printf("vdp_port write: %X, value: %X, cycle: %d\n", vdp_port, value, context->current_cycle); |
313 sync_components(context, 0); | 313 sync_components(context, 0); |
314 vdp_context * v_context = context->video_context; | 314 vdp_context * v_context = context->video_context; |
315 genesis_context * gen = context->system; | |
315 if (vdp_port < 0x10) { | 316 if (vdp_port < 0x10) { |
316 int blocked; | 317 int blocked; |
317 uint32_t before_cycle = v_context->cycles; | 318 uint32_t before_cycle = v_context->cycles; |
318 if (vdp_port < 4) { | 319 if (vdp_port < 4) { |
320 gen->bus_busy = 1; | |
319 while (vdp_data_port_write(v_context, value) < 0) { | 321 while (vdp_data_port_write(v_context, value) < 0) { |
320 while(v_context->flags & FLAG_DMA_RUN) { | 322 while(v_context->flags & FLAG_DMA_RUN) { |
321 vdp_run_dma_done(v_context, mclks_per_frame); | 323 vdp_run_dma_done(v_context, mclks_per_frame); |
322 if (v_context->cycles >= mclks_per_frame) { | 324 if (v_context->cycles >= mclks_per_frame) { |
323 if (!headless) { | 325 if (!headless) { |
345 } | 347 } |
346 } | 348 } |
347 //context->current_cycle = v_context->cycles / MCLKS_PER_68K; | 349 //context->current_cycle = v_context->cycles / MCLKS_PER_68K; |
348 } | 350 } |
349 } else if(vdp_port < 8) { | 351 } else if(vdp_port < 8) { |
352 gen->bus_busy = 1; | |
350 blocked = vdp_control_port_write(v_context, value); | 353 blocked = vdp_control_port_write(v_context, value); |
351 if (blocked) { | 354 if (blocked) { |
352 while (blocked) { | 355 while (blocked) { |
353 while(v_context->flags & FLAG_DMA_RUN) { | 356 while(v_context->flags & FLAG_DMA_RUN) { |
354 vdp_run_dma_done(v_context, mclks_per_frame); | 357 vdp_run_dma_done(v_context, mclks_per_frame); |
392 if (v_context->cycles != before_cycle) { | 395 if (v_context->cycles != before_cycle) { |
393 //printf("68K paused for %d (%d) cycles at cycle %d (%d) for write\n", v_context->cycles / MCLKS_PER_68K - context->current_cycle, v_context->cycles - before_cycle, context->current_cycle, before_cycle); | 396 //printf("68K paused for %d (%d) cycles at cycle %d (%d) for write\n", v_context->cycles / MCLKS_PER_68K - context->current_cycle, v_context->cycles - before_cycle, context->current_cycle, before_cycle); |
394 context->current_cycle = v_context->cycles / MCLKS_PER_68K; | 397 context->current_cycle = v_context->cycles / MCLKS_PER_68K; |
395 } | 398 } |
396 } else if (vdp_port < 0x18) { | 399 } else if (vdp_port < 0x18) { |
397 genesis_context * gen = context->system; | |
398 sync_sound(gen, context->current_cycle * MCLKS_PER_68K); | 400 sync_sound(gen, context->current_cycle * MCLKS_PER_68K); |
399 psg_write(gen->psg, value); | 401 psg_write(gen->psg, value); |
400 } else { | 402 } else { |
401 //TODO: Implement undocumented test register(s) | 403 //TODO: Implement undocumented test register(s) |
404 } | |
405 if (gen->bus_busy) | |
406 { | |
407 //Lock the Z80 out of the bus until the VDP access is complete | |
408 sync_z80(gen->z80, v_context->cycles); | |
409 gen->bus_busy = 0; | |
402 } | 410 } |
403 return context; | 411 return context; |
404 } | 412 } |
405 | 413 |
406 m68k_context * vdp_port_write_b(uint32_t vdp_port, m68k_context * context, uint8_t value) | 414 m68k_context * vdp_port_write_b(uint32_t vdp_port, m68k_context * context, uint8_t value) |