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comparison m68k_to_x86.c @ 123:bd3858121ab0

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Implement the rest of the bit instructions
author Mike Pavone <pavone@retrodev.com>
date Sat, 29 Dec 2012 21:10:07 -0800
parents 0a6da6c7c463
children da95566514f3
comparison
equal deleted inserted replaced
122:0a6da6c7c463 123:bd3858121ab0
2073 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL); 2073 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL);
2074 break; 2074 break;
2075 case M68K_LSR: 2075 case M68K_LSR:
2076 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8); 2076 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8);
2077 break; 2077 break;
2078 /*case M68K_BCHG: 2078 case M68K_BCHG:
2079 case M68K_BCLR: 2079 case M68K_BCLR:
2080 case M68K_BSET: 2080 case M68K_BSET:
2081 break;*/
2082 case M68K_BTST: 2081 case M68K_BTST:
2083 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6); 2082 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6);
2084 if (src_op.mode == MODE_IMMED) { 2083 if (src_op.mode == MODE_IMMED) {
2085 if (inst->extra.size == OPSIZE_BYTE) { 2084 if (inst->extra.size == OPSIZE_BYTE) {
2086 src_op.disp &= 0x7; 2085 src_op.disp &= 0x7;
2087 } 2086 }
2088 if (dst_op.mode == MODE_REG_DIRECT) { 2087 if (inst->op == M68K_BTST) {
2089 dst = bt_ir(dst, src_op.disp, dst_op.base, SZ_D); 2088 if (dst_op.mode == MODE_REG_DIRECT) {
2090 } else { 2089 dst = bt_ir(dst, src_op.disp, dst_op.base, SZ_D);
2091 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D); 2090 } else {
2091 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
2092 }
2093 } else if (inst->op == M68K_BSET) {
2094 if (dst_op.mode == MODE_REG_DIRECT) {
2095 dst = bts_ir(dst, src_op.disp, dst_op.base, SZ_D);
2096 } else {
2097 dst = bts_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
2098 }
2099 } else if (inst->op == M68K_BCLR) {
2100 if (dst_op.mode == MODE_REG_DIRECT) {
2101 dst = btr_ir(dst, src_op.disp, dst_op.base, SZ_D);
2102 } else {
2103 dst = btr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
2104 }
2105 } else {
2106 if (dst_op.mode == MODE_REG_DIRECT) {
2107 dst = btc_ir(dst, src_op.disp, dst_op.base, SZ_D);
2108 } else {
2109 dst = btc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
2110 }
2092 } 2111 }
2093 } else { 2112 } else {
2094 if (src_op.mode == MODE_REG_DISPLACE8) { 2113 if (src_op.mode == MODE_REG_DISPLACE8) {
2095 if (dst_op.base == SCRATCH1) { 2114 if (dst_op.base == SCRATCH1) {
2096 dst = push_r(dst, SCRATCH2); 2115 dst = push_r(dst, SCRATCH2);
2102 } 2121 }
2103 } 2122 }
2104 if (inst->extra.size == OPSIZE_BYTE) { 2123 if (inst->extra.size == OPSIZE_BYTE) {
2105 dst = and_ir(dst, 0x7, src_op.base, SZ_B); 2124 dst = and_ir(dst, 0x7, src_op.base, SZ_B);
2106 } 2125 }
2107 if (dst_op.mode == MODE_REG_DIRECT) { 2126 if (inst->op == M68K_BTST) {
2108 dst = bt_rr(dst, src_op.base, dst_op.base, SZ_D); 2127 if (dst_op.mode == MODE_REG_DIRECT) {
2109 } else { 2128 dst = bt_rr(dst, src_op.base, dst_op.base, SZ_D);
2110 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D); 2129 } else {
2130 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
2131 }
2132 } else if (inst->op == M68K_BSET) {
2133 if (dst_op.mode == MODE_REG_DIRECT) {
2134 dst = bts_rr(dst, src_op.base, dst_op.base, SZ_D);
2135 } else {
2136 dst = bts_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
2137 }
2138 } else if (inst->op == M68K_BCLR) {
2139 if (dst_op.mode == MODE_REG_DIRECT) {
2140 dst = btr_rr(dst, src_op.base, dst_op.base, SZ_D);
2141 } else {
2142 dst = btr_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
2143 }
2144 } else {
2145 if (dst_op.mode == MODE_REG_DIRECT) {
2146 dst = btc_rr(dst, src_op.base, dst_op.base, SZ_D);
2147 } else {
2148 dst = btc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
2149 }
2111 } 2150 }
2112 } 2151 }
2113 //x86 sets the carry flag to the value of the bit tested 2152 //x86 sets the carry flag to the value of the bit tested
2114 //68K sets the zero flag to the complement of the bit tested 2153 //68K sets the zero flag to the complement of the bit tested
2115 dst = setcc_r(dst, CC_NC, FLAG_Z); 2154 dst = setcc_r(dst, CC_NC, FLAG_Z);