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comparison z80_to_x86.c @ 310:bf440db64086

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Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
author Mike Pavone <pavone@retrodev.com>
date Thu, 09 May 2013 00:30:55 -0700
parents cb6a37861e42
children 56fcbfb8767a
comparison
equal deleted inserted replaced
309:cb6a37861e42 310:bf440db64086
1014 } else { 1014 } else {
1015 src_op.mode = MODE_UNUSED; 1015 src_op.mode = MODE_UNUSED;
1016 dst = translate_z80_reg(inst, &dst_op, dst, opts); 1016 dst = translate_z80_reg(inst, &dst_op, dst, opts);
1017 } 1017 }
1018 dst = shl_ir(dst, 1, dst_op.base, SZ_B); 1018 dst = shl_ir(dst, 1, dst_op.base, SZ_B);
1019 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
1020 if (inst->op == Z80_SLL) {
1021 dst = or_ir(dst, 1, dst_op.base, SZ_B);
1022 }
1019 if (src_op.mode != MODE_UNUSED) { 1023 if (src_op.mode != MODE_UNUSED) {
1020 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); 1024 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
1021 } 1025 }
1022 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); 1026 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
1023 //TODO: Implement half-carry flag 1027 //TODO: Implement half-carry flag
1047 } 1051 }
1048 dst = sar_ir(dst, 1, dst_op.base, SZ_B); 1052 dst = sar_ir(dst, 1, dst_op.base, SZ_B);
1049 if (src_op.mode != MODE_UNUSED) { 1053 if (src_op.mode != MODE_UNUSED) {
1050 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); 1054 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
1051 } 1055 }
1056 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
1052 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); 1057 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
1053 //TODO: Implement half-carry flag 1058 //TODO: Implement half-carry flag
1054 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); 1059 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
1055 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); 1060 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
1056 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); 1061 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
1077 } 1082 }
1078 dst = shr_ir(dst, 1, dst_op.base, SZ_B); 1083 dst = shr_ir(dst, 1, dst_op.base, SZ_B);
1079 if (src_op.mode != MODE_UNUSED) { 1084 if (src_op.mode != MODE_UNUSED) {
1080 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); 1085 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
1081 } 1086 }
1087 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
1082 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); 1088 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
1083 //TODO: Implement half-carry flag 1089 //TODO: Implement half-carry flag
1084 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); 1090 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
1085 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); 1091 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
1086 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); 1092 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
1091 dst = z80_save_reg(dst, inst, opts); 1097 dst = z80_save_reg(dst, inst, opts);
1092 } 1098 }
1093 } else { 1099 } else {
1094 dst = z80_save_reg(dst, inst, opts); 1100 dst = z80_save_reg(dst, inst, opts);
1095 } 1101 }
1102 break;
1096 case Z80_RLD: 1103 case Z80_RLD:
1097 dst = zcycles(dst, 8); 1104 dst = zcycles(dst, 8);
1098 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); 1105 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W);
1099 dst = call(dst, (uint8_t *)z80_read_byte); 1106 dst = call(dst, (uint8_t *)z80_read_byte);
1100 //Before: (HL) = 0x12, A = 0x34 1107 //Before: (HL) = 0x12, A = 0x34