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Initial work on handling the 128KB VRAM mode bit and some basic prep work for VDP test register support
author Michael Pavone <pavone@retrodev.com>
date Sun, 16 Apr 2017 16:40:04 -0700
parents 810ae0287d66
children b6796d63977f
comparison
equal deleted inserted replaced
1317:32e95d6733a6 1318:bfdd450e7dea
755 context->flags &= ~FLAG_DMA_RUN; 755 context->flags &= ~FLAG_DMA_RUN;
756 context->cd &= 0xF; 756 context->cd &= 0xF;
757 } 757 }
758 } 758 }
759 759
760 void write_vram_byte(vdp_context *context, uint16_t address, uint8_t value) 760 void write_vram_byte(vdp_context *context, uint32_t address, uint8_t value)
761 { 761 {
762 if (context->regs[REG_MODE_2] & BIT_MODE_5) { 762 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
763 if (context->regs[REG_MODE_2] & BIT_128K_VRAM) {
764 address = (address & 0x3FC) | (address >> 1 & 0xFC01) | (address >> 9 & 0x2);
765 address ^= 1;
766 } else {
767 address &= 0xFFFF;
768 }
763 if (!(address & 4)) { 769 if (!(address & 4)) {
764 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; 770 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9;
765 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) { 771 if(address >= sat_address && address < (sat_address + SAT_CACHE_SIZE*2)) {
766 uint16_t cache_address = address - sat_address; 772 uint16_t cache_address = address - sat_address;
767 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC); 773 cache_address = (cache_address & 3) | (cache_address >> 1 & 0x1FC);
787 fifo_entry * start = context->fifo + context->fifo_read; 793 fifo_entry * start = context->fifo + context->fifo_read;
788 if (context->fifo_read >= 0 && start->cycle <= context->cycles) { 794 if (context->fifo_read >= 0 && start->cycle <= context->cycles) {
789 switch (start->cd & 0xF) 795 switch (start->cd & 0xF)
790 { 796 {
791 case VRAM_WRITE: 797 case VRAM_WRITE:
792 if (start->partial) { 798 //TODO: Support actually having 128K VRAM as an option
799 if (start->partial || (context->regs[REG_MODE_2] & BIT_128K_VRAM)) {
793 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); 800 //printf("VRAM Write: %X to %X at %d (line %d, slot %d)\n", start->value, start->address ^ 1, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
794 write_vram_byte(context, start->address ^ 1, start->partial == 2 ? start->value >> 8 : start->value); 801 write_vram_byte(context, start->address ^ 1, start->partial == 2 ? start->value >> 8 : start->value);
795 } else { 802 } else {
796 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16); 803 //printf("VRAM Write High: %X to %X at %d (line %d, slot %d)\n", start->value >> 8, start->address, context->cycles, context->cycles/MCLKS_LINE, (context->cycles%MCLKS_LINE)/16);
797 write_vram_byte(context, start->address, start->value >> 8); 804 write_vram_byte(context, start->address, start->value >> 8);
863 context->flags |= FLAG_READ_FETCHED; 870 context->flags |= FLAG_READ_FETCHED;
864 context->flags2 &= ~FLAG2_READ_PENDING; 871 context->flags2 &= ~FLAG2_READ_PENDING;
865 //Should this happen after the prefetch or after the read? 872 //Should this happen after the prefetch or after the read?
866 increment_address(context); 873 increment_address(context);
867 } else { 874 } else {
875 //TODO: 128K VRAM Mode
868 context->prefetch = context->vdpmem[context->address & 0xFFFE] << 8; 876 context->prefetch = context->vdpmem[context->address & 0xFFFE] << 8;
869 context->flags2 |= FLAG2_READ_PENDING; 877 context->flags2 |= FLAG2_READ_PENDING;
870 } 878 }
871 break; 879 break;
872 case VRAM_READ8: { 880 case VRAM_READ8: {
2454 //printf("control port write: %X at %d\n", value, context->cycles); 2462 //printf("control port write: %X at %d\n", value, context->cycles);
2455 if (context->flags & FLAG_DMA_RUN) { 2463 if (context->flags & FLAG_DMA_RUN) {
2456 return -1; 2464 return -1;
2457 } 2465 }
2458 if (context->flags & FLAG_PENDING) { 2466 if (context->flags & FLAG_PENDING) {
2459 context->address = (context->address & 0x3FFF) | (value << 14); 2467 context->address = (context->address & 0x3FFF) | (value << 14 & 0x1C000);
2460 //It seems like the DMA enable bit doesn't so much enable DMA so much 2468 //It seems like the DMA enable bit doesn't so much enable DMA so much
2461 //as it enables changing CD5 from control port writes 2469 //as it enables changing CD5 from control port writes
2462 uint8_t preserve = (context->regs[REG_MODE_2] & BIT_DMA_ENABLE) ? 0x3 : 0x23; 2470 uint8_t preserve = (context->regs[REG_MODE_2] & BIT_DMA_ENABLE) ? 0x3 : 0x23;
2463 context->cd = (context->cd & preserve) | ((value >> 2) & ~preserve & 0xFF); 2471 context->cd = (context->cd & preserve) | ((value >> 2) & ~preserve & 0xFF);
2464 context->flags &= ~FLAG_PENDING; 2472 context->flags &= ~FLAG_PENDING;
2621 increment_address(context); 2629 increment_address(context);
2622 } 2630 }
2623 2631
2624 void vdp_test_port_write(vdp_context * context, uint16_t value) 2632 void vdp_test_port_write(vdp_context * context, uint16_t value)
2625 { 2633 {
2626 //TODO: implement test register 2634 context->test_port = value;
2627 } 2635 }
2628 2636
2629 uint16_t vdp_control_port_read(vdp_context * context) 2637 uint16_t vdp_control_port_read(vdp_context * context)
2630 { 2638 {
2631 context->flags &= ~FLAG_PENDING; 2639 context->flags &= ~FLAG_PENDING;
2704 } 2712 }
2705 2713
2706 uint16_t vdp_test_port_read(vdp_context * context) 2714 uint16_t vdp_test_port_read(vdp_context * context)
2707 { 2715 {
2708 //TODO: Find out what actually gets returned here 2716 //TODO: Find out what actually gets returned here
2709 return 0xFFFF; 2717 return context->test_port;
2710 } 2718 }
2711 2719
2712 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) 2720 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction)
2713 { 2721 {
2714 context->cycles -= deduction; 2722 context->cycles -= deduction;