Mercurial > repos > blastem

comparison m68k_to_x86.c @ 169:c07713463c91

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Fix a bunch of addressing modes in movem when a register list is the destination
author Mike Pavone <pavone@retrodev.com>
date Sun, 06 Jan 2013 13:42:13 -0800
parents 7b099f2b382b
children 7d1b04537377
comparison
equal deleted inserted replaced
168:7b099f2b382b 169:c07713463c91
1153 } 1153 }
1154 break; 1154 break;
1155 case MODE_AREG_DISPLACE: 1155 case MODE_AREG_DISPLACE:
1156 early_cycles += BUS; 1156 early_cycles += BUS;
1157 reg = SCRATCH2; 1157 reg = SCRATCH2;
1158 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { 1158 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
1159 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); 1159 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
1160 } else { 1160 } else {
1161 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); 1161 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
1162 } 1162 }
1163 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); 1163 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
1164 break; 1164 break;
1165 case MODE_AREG_INDEX_DISP8: 1165 case MODE_AREG_INDEX_DISP8:
1166 early_cycles += 6; 1166 early_cycles += 6;
1167 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { 1167 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
1168 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D); 1168 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
1169 } else { 1169 } else {
1170 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D); 1170 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
1171 } 1171 }
1172 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; 1172 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
1173 if (inst->dst.params.regs.sec & 1) { 1173 if (inst->src.params.regs.sec & 1) {
1174 if (inst->dst.params.regs.sec & 0x10) { 1174 if (inst->src.params.regs.sec & 0x10) {
1175 if (opts->aregs[sec_reg] >= 0) { 1175 if (opts->aregs[sec_reg] >= 0) {
1176 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); 1176 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
1177 } else { 1177 } else {
1178 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); 1178 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
1179 } 1179 }
1183 } else { 1183 } else {
1184 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); 1184 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
1185 } 1185 }
1186 } 1186 }
1187 } else { 1187 } else {
1188 if (inst->dst.params.regs.sec & 0x10) { 1188 if (inst->src.params.regs.sec & 0x10) {
1189 if (opts->aregs[sec_reg] >= 0) { 1189 if (opts->aregs[sec_reg] >= 0) {
1190 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); 1190 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
1191 } else { 1191 } else {
1192 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); 1192 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
1193 } 1193 }
1198 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); 1198 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
1199 } 1199 }
1200 } 1200 }
1201 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); 1201 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
1202 } 1202 }
1203 if (inst->dst.params.regs.displacement) { 1203 if (inst->src.params.regs.displacement) {
1204 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); 1204 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
1205 } 1205 }
1206 break; 1206 break;
1207 case MODE_PC_DISPLACE: 1207 case MODE_PC_DISPLACE:
1208 early_cycles += BUS; 1208 early_cycles += BUS;
1209 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D); 1209 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
1210 break; 1210 break;
1211 case MODE_PC_INDEX_DISP8: 1211 case MODE_PC_INDEX_DISP8:
1212 early_cycles += 6; 1212 early_cycles += 6;
1213 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); 1213 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
1214 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7; 1214 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
1215 if (inst->dst.params.regs.sec & 1) { 1215 if (inst->src.params.regs.sec & 1) {
1216 if (inst->dst.params.regs.sec & 0x10) { 1216 if (inst->src.params.regs.sec & 0x10) {
1217 if (opts->aregs[sec_reg] >= 0) { 1217 if (opts->aregs[sec_reg] >= 0) {
1218 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D); 1218 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
1219 } else { 1219 } else {
1220 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); 1220 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
1221 } 1221 }
1225 } else { 1225 } else {
1226 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D); 1226 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
1227 } 1227 }
1228 } 1228 }
1229 } else { 1229 } else {
1230 if (inst->dst.params.regs.sec & 0x10) { 1230 if (inst->src.params.regs.sec & 0x10) {
1231 if (opts->aregs[sec_reg] >= 0) { 1231 if (opts->aregs[sec_reg] >= 0) {
1232 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D); 1232 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
1233 } else { 1233 } else {
1234 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); 1234 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
1235 } 1235 }
1240 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D); 1240 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
1241 } 1241 }
1242 } 1242 }
1243 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D); 1243 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
1244 } 1244 }
1245 if (inst->dst.params.regs.displacement) { 1245 if (inst->src.params.regs.displacement) {
1246 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D); 1246 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
1247 } 1247 }
1248 break; 1248 break;
1249 case MODE_ABSOLUTE: 1249 case MODE_ABSOLUTE:
1250 early_cycles += 4; 1250 early_cycles += 4;
1251 case MODE_ABSOLUTE_SHORT: 1251 case MODE_ABSOLUTE_SHORT: