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Fix V flag for asl in new CPU core
author Michael Pavone <pavone@retrodev.com>
date Sat, 22 Feb 2025 01:31:51 -0800
parents 1579b840a1af
children adff015dc94f
comparison
equal deleted inserted replaced
2620:b58ca7af1e60 2621:ce9386a7b21e
1730 m68k_save_dst 0 1730 m68k_save_dst 0
1731 m68k_prefetch 1731 m68k_prefetch
1732 1732
1733 1110CCC1ZZ000RRR asli 1733 1110CCC1ZZ000RRR asli
1734 invalid Z 3 1734 invalid Z 3
1735 local vtmp 8
1736 local shift 8
1737 vtmp = 0
1735 switch C 1738 switch C
1736 case 0 1739 case 0
1737 meta shift 8 1740 shift = 8
1738 default 1741 default
1739 meta shift C 1742 shift = C
1740 end 1743 end
1741 lsl dregs.R shift dregs.R Z 1744 shift -= 1
1742 update_flags XNZV0C 1745 loop shift
1746 lsl dregs.R 1 dregs.R Z
1747 update_flags V
1748 vtmp |= vflag
1749 end
1750 shift += 1
1751 lsl dregs.R 1 dregs.R Z
1752 update_flags XNZVC
1753 vflag |= vtmp
1743 local cyc 32 1754 local cyc 32
1744 cyc = shift + shift 1755 cyc = shift + shift
1745 switch Z 1756 switch Z
1746 case 2 1757 case 2
1747 cyc += 4 1758 cyc += 4
1753 m68k_prefetch 1764 m68k_prefetch
1754 1765
1755 1110CCC1ZZ100RRR asl_dn 1766 1110CCC1ZZ100RRR asl_dn
1756 invalid Z 3 1767 invalid Z 3
1757 local shift 8 1768 local shift 8
1769 local vtmp 8
1758 and dregs.C 63 shift 1770 and dregs.C 63 shift
1759 #TODO: implement loops and do this a bit at a time to implement V flag 1771 vtmp = 0
1760 switch Z 1772 if shift
1761 case 2 1773 shift -= 1
1762 if shift >=U 32 1774 loop shift
1763 if shift = 32 1775 lsl dregs.R 1 dregs.R Z
1764 lsl dregs.R 31 dregs.R Z 1776 update_flags V
1765 lsl dregs.R 1 dregs.R Z 1777 vtmp |= vflag
1766 update_flags XNZ1V0C 1778 end
1767 else 1779 shift += 1
1768 dregs.R:Z = 0 1780 lsl dregs.R 1 dregs.R Z
1769 update_flags X0N0Z1V0C0 1781 update_flags XNZVC
1770 end 1782 vflag |= vtmp
1771 else 1783 else
1772 lsl dregs.R shift dregs.R Z 1784 cmp 0 dregs.R Z
1773 update_flags NZV0C 1785 update_flags NZV0C
1774 if shift 1786 end
1775 xflag = cflag 1787 shift += shift
1776 end 1788 switch Z
1777 end 1789 case 2
1778 case 1 1790 shift += 4
1779 if shift >=U 16 1791 default
1780 if shift = 16 1792 shift += 2
1781 lsl dregs.R 15 dregs.R Z
1782 lsl dregs.R 1 dregs.R Z
1783 update_flags XN0Z1V0C
1784 else
1785 dregs.R:Z = 0
1786 update_flags X0N0Z1V0C0
1787 end
1788 else
1789 lsl dregs.R shift dregs.R Z
1790 update_flags NZV0C
1791 if shift
1792 xflag = cflag
1793 end
1794 end
1795 case 0
1796 if shift >=U 8
1797 if shift = 8
1798 lsl dregs.R 7 dregs.R Z
1799 lsl dregs.R 1 dregs.R Z
1800 update_flags XN0Z1V0C
1801 else
1802 dregs.R:Z = 0
1803 update_flags X0N0Z1V0C0
1804 end
1805 else
1806 lsl dregs.R shift dregs.R Z
1807 update_flags NZV0C
1808 if shift
1809 xflag = cflag
1810 end
1811 end
1812 end
1813 add shift shift shift
1814 switch Z
1815 case 2
1816 add 4 shift shift
1817 default
1818 add 2 shift shift
1819 end 1793 end
1820 cycles shift 1794 cycles shift
1821 #TODO: should this happen before or after the majority of the shift? 1795 #TODO: should this happen before or after the majority of the shift?
1822 m68k_prefetch 1796 m68k_prefetch
1823 1797