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comparison z80_to_x86.c @ 1110:d1eed3b1121c

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Fix a couple of timing regressions in Z80 core
author Michael Pavone <pavone@retrodev.com>
date Wed, 14 Dec 2016 23:27:42 -0800
parents 779acbfb74d0
children fe8c79f82c22
comparison
equal deleted inserted replaced
1109:4bc27caa6e20 1110:d1eed3b1121c
361 case Z80_IMMED_INDIRECT: 361 case Z80_IMMED_INDIRECT:
362 num_cycles += 6; 362 num_cycles += 6;
363 break; 363 break;
364 case Z80_IX_DISPLACE: 364 case Z80_IX_DISPLACE:
365 case Z80_IY_DISPLACE: 365 case Z80_IY_DISPLACE:
366 num_cycles = 8; //3 for displacement, 5 for address addition 366 num_cycles += 8; //3 for displacement, 5 for address addition
367 break; 367 break;
368 } 368 }
369 cycles(&opts->gen, num_cycles); 369 cycles(&opts->gen, num_cycles);
370 if (inst->addr_mode & Z80_DIR) { 370 if (inst->addr_mode & Z80_DIR) {
371 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY); 371 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY);
1415 } 1415 }
1416 case Z80_DI: 1416 case Z80_DI:
1417 cycles(&opts->gen, num_cycles); 1417 cycles(&opts->gen, num_cycles);
1418 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); 1418 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
1419 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B); 1419 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
1420 //turn cycles remaining into current cycle
1421 neg_r(code, opts->gen.cycles, SZ_D);
1420 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D); 1422 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D);
1423 //set interrupt cycle to never and fetch the new target cycle from sync_cycle
1421 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.scratch1, SZ_D); 1424 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.scratch1, SZ_D);
1422 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D); 1425 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D);
1423 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D); 1426 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D);
1424 sub_rr(code, opts->gen.scratch1, opts->gen.cycles, SZ_D); 1427 //turn current cycle back into cycles remaining
1428 neg_r(code, opts->gen.cycles, SZ_D);
1429 add_rr(code, opts->gen.scratch1, opts->gen.cycles, SZ_D);
1425 break; 1430 break;
1426 case Z80_EI: 1431 case Z80_EI:
1427 cycles(&opts->gen, num_cycles); 1432 cycles(&opts->gen, num_cycles);
1428 neg_r(code, opts->gen.cycles, SZ_D); 1433 neg_r(code, opts->gen.cycles, SZ_D);
1429 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D); 1434 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D);