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comparison m68k.cpu @ 2587:e04c7e753bf6

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Implement divs and divu in new CPU core
author Michael Pavone <pavone@retrodev.com>
date Sat, 08 Feb 2025 20:04:18 -0800
parents 6c58cadeabe1
children 0ea26288d983
comparison
equal deleted inserted replaced
2586:6c58cadeabe1 2587:e04c7e753bf6
1001 scratch1 = prefetch >> 8 1001 scratch1 = prefetch >> 8
1002 status |= scratch1 1002 status |= scratch1
1003 update_sync 1003 update_sync
1004 cycles 12 #TODO: where do these occur relative to fetches 1004 cycles 12 #TODO: where do these occur relative to fetches
1005 m68k_prefetch 1005 m68k_prefetch
1006
1007 1000DDD011MMMRRR divu
1008 invalid M 1
1009 invalid M 7 R 5
1010 invalid M 7 R 6
1011 invalid M 7 R 7
1012 m68k_fetch_src_ea M R 1
1013
1014 if src = 0
1015 cycles 4
1016 update_flags N0Z0V0
1017 m68k_trap 5
1018 else
1019 ccall divu context D src
1020 m68k_prefetch
1021 end
1022
1023
1024 1000DDD111MMMRRR divs
1025 invalid M 1
1026 invalid M 7 R 5
1027 invalid M 7 R 6
1028 invalid M 7 R 7
1029 local tmp 32
1030 m68k_fetch_src_ea M R 1
1031
1032 if src = 0
1033 cycles 4
1034 update_flags N0Z0V0
1035 m68k_trap 5
1036 else
1037 ccall divs context D src
1038 m68k_prefetch
1039 end
1006 1040
1007 1001DDD0ZZMMMRRR sub_ea_dn 1041 1001DDD0ZZMMMRRR sub_ea_dn
1008 invalid M 7 R 5 1042 invalid M 7 R 5
1009 invalid M 7 R 6 1043 invalid M 7 R 6
1010 invalid M 7 R 7 1044 invalid M 7 R 7