Mercurial > repos > blastem

comparison z80_to_x86.c @ 734:e21c274a008e

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Fix RLD and RRD for the case in which HL does not map to a native register
author Michael Pavone <pavone@retrodev.com>
date Mon, 25 May 2015 17:08:56 -0700
parents 0835cd3dfc36
children 539d12fa6a4d
comparison
equal deleted inserted replaced
733:fbda8e865dae 734:e21c274a008e
1395 z80_save_reg(inst, opts); 1395 z80_save_reg(inst, opts);
1396 } 1396 }
1397 break; 1397 break;
1398 case Z80_RLD: 1398 case Z80_RLD:
1399 cycles(&opts->gen, 8); 1399 cycles(&opts->gen, 8);
1400 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); 1400 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
1401 call(code, opts->read_8); 1401 call(code, opts->read_8);
1402 //Before: (HL) = 0x12, A = 0x34 1402 //Before: (HL) = 0x12, A = 0x34
1403 //After: (HL) = 0x24, A = 0x31 1403 //After: (HL) = 0x24, A = 0x31
1404 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); 1404 zreg_to_native(opts, Z80_A, opts->gen.scratch2);
1405 shl_ir(code, 4, opts->gen.scratch1, SZ_W); 1405 shl_ir(code, 4, opts->gen.scratch1, SZ_W);
1406 and_ir(code, 0xF, opts->gen.scratch2, SZ_W); 1406 and_ir(code, 0xF, opts->gen.scratch2, SZ_W);
1407 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W); 1407 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W);
1408 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); 1408 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
1409 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); 1409 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
1416 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); 1416 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1417 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); 1417 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
1418 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); 1418 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
1419 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); 1419 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1420 1420
1421 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W); 1421 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
1422 ror_ir(code, 8, opts->gen.scratch1, SZ_W); 1422 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
1423 call(code, opts->write_8); 1423 call(code, opts->write_8);
1424 break; 1424 break;
1425 case Z80_RRD: 1425 case Z80_RRD:
1426 cycles(&opts->gen, 8); 1426 cycles(&opts->gen, 8);
1427 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W); 1427 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
1428 call(code, opts->read_8); 1428 call(code, opts->read_8);
1429 //Before: (HL) = 0x12, A = 0x34 1429 //Before: (HL) = 0x12, A = 0x34
1430 //After: (HL) = 0x41, A = 0x32 1430 //After: (HL) = 0x41, A = 0x32
1431 movzx_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B, SZ_W); 1431 zreg_to_native(opts, Z80_A, opts->gen.scratch2);
1432 ror_ir(code, 4, opts->gen.scratch1, SZ_W); 1432 ror_ir(code, 4, opts->gen.scratch1, SZ_W);
1433 shl_ir(code, 4, opts->gen.scratch2, SZ_W); 1433 shl_ir(code, 4, opts->gen.scratch2, SZ_W);
1434 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W); 1434 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W);
1435 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); 1435 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
1436 //opts->gen.scratch1 = 0x2001 1436 //opts->gen.scratch1 = 0x2001
1446 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); 1446 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1447 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); 1447 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
1448 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); 1448 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
1449 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); 1449 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1450 1450
1451 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W); 1451 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
1452 ror_ir(code, 8, opts->gen.scratch1, SZ_W); 1452 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
1453 call(code, opts->write_8); 1453 call(code, opts->write_8);
1454 break; 1454 break;
1455 case Z80_BIT: { 1455 case Z80_BIT: {
1456 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; 1456 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;