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comparison m68k_core_x86.c @ 2225:e22137f0aca4

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Fix some 68K exception processing cycle times
author Michael Pavone <pavone@retrodev.com>
date Mon, 05 Sep 2022 01:15:15 -0700
parents d8b0244101c4
children d15c68157288
comparison
equal deleted inserted replaced
2224:d8b0244101c4 2225:e22137f0aca4
1706 } 1706 }
1707 1707
1708 void translate_m68k_chk(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) 1708 void translate_m68k_chk(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op)
1709 { 1709 {
1710 code_info *code = &opts->gen.code; 1710 code_info *code = &opts->gen.code;
1711 cycles(&opts->gen, 6); 1711 cycles(&opts->gen, 4);
1712 if (dst_op->mode == MODE_REG_DIRECT) { 1712 if (dst_op->mode == MODE_REG_DIRECT) {
1713 cmp_ir(code, 0, dst_op->base, inst->extra.size); 1713 cmp_ir(code, 0, dst_op->base, inst->extra.size);
1714 } else { 1714 } else {
1715 cmp_irdisp(code, 0, dst_op->base, dst_op->disp, inst->extra.size); 1715 cmp_irdisp(code, 0, dst_op->base, dst_op->disp, inst->extra.size);
1716 } 1716 }
1760 set_flag(opts, 0, FLAG_N); 1760 set_flag(opts, 0, FLAG_N);
1761 mov_ir(code, VECTOR_CHK, opts->gen.scratch2, SZ_D); 1761 mov_ir(code, VECTOR_CHK, opts->gen.scratch2, SZ_D);
1762 mov_ir(code, inst->address+isize, opts->gen.scratch1, SZ_D); 1762 mov_ir(code, inst->address+isize, opts->gen.scratch1, SZ_D);
1763 jmp(code, opts->trap); 1763 jmp(code, opts->trap);
1764 *passed = code->cur - (passed+1); 1764 *passed = code->cur - (passed+1);
1765 cycles(&opts->gen, 4); 1765 cycles(&opts->gen, 6);
1766 } 1766 }
1767 1767
1768 static uint32_t divu(uint32_t dividend, m68k_context *context, uint32_t divisor_shift) 1768 static uint32_t divu(uint32_t dividend, m68k_context *context, uint32_t divisor_shift)
1769 { 1769 {
1770 uint16_t quotient = 0; 1770 uint16_t quotient = 0;
3205 //calculate vector address 3205 //calculate vector address
3206 pop_r(code, opts->gen.scratch1); 3206 pop_r(code, opts->gen.scratch1);
3207 shl_ir(code, 2, opts->gen.scratch1, SZ_D); 3207 shl_ir(code, 2, opts->gen.scratch1, SZ_D);
3208 call(code, opts->read_32); 3208 call(code, opts->read_32);
3209 call(code, opts->native_addr_and_sync); 3209 call(code, opts->native_addr_and_sync);
3210 cycles(&opts->gen, 18); 3210 cycles(&opts->gen, 14);
3211 jmp_r(code, opts->gen.scratch1); 3211 jmp_r(code, opts->gen.scratch1);
3212 3212
3213 opts->retrans_stub = code->cur; 3213 opts->retrans_stub = code->cur;
3214 call(code, opts->gen.save_context); 3214 call(code, opts->gen.save_context);
3215 push_r(code, opts->gen.context_reg); 3215 push_r(code, opts->gen.context_reg);