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comparison backend_x86.c @ 590:ea80559c67cb

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WIP effort to update z80 core for code gen changes
author Michael Pavone <pavone@retrodev.com>
date Sun, 14 Dec 2014 16:45:23 -0800
parents 2dde38c1744f
children 5ef3fe516da9
comparison
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589:2dde38c1744f 590:ea80559c67cb
26 jcc(code, CC_NC, jmp_off+1); 26 jcc(code, CC_NC, jmp_off+1);
27 call(code, opts->handle_cycle_limit); 27 call(code, opts->handle_cycle_limit);
28 *jmp_off = code->cur - (jmp_off+1); 28 *jmp_off = code->cur - (jmp_off+1);
29 } 29 }
30 30
31 code_ptr gen_mem_fun(cpu_options * opts, memmap_chunk * memmap, uint32_t num_chunks, ftype fun_type) 31 code_ptr gen_mem_fun(cpu_options * opts, memmap_chunk * memmap, uint32_t num_chunks, ftype fun_type, code_ptr *after_inc)
32 { 32 {
33 code_info *code = &opts->code; 33 code_info *code = &opts->code;
34 code_ptr start = code->cur; 34 code_ptr start = code->cur;
35 check_cycles(opts); 35 check_cycles(opts);
36 cycles(opts, opts->bus_cycles); 36 cycles(opts, opts->bus_cycles);
37 if (after_inc) {
38 *after_inc = code->cur;
39 }
37 if (opts->address_size == SZ_D && opts->address_mask < 0xFFFFFFFF) { 40 if (opts->address_size == SZ_D && opts->address_mask < 0xFFFFFFFF) {
38 and_ir(code, opts->address_mask, opts->scratch1, SZ_D); 41 and_ir(code, opts->address_mask, opts->scratch1, SZ_D);
39 } 42 }
40 code_ptr lb_jcc = NULL, ub_jcc = NULL; 43 code_ptr lb_jcc = NULL, ub_jcc = NULL;
41 uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8; 44 uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8;