Mercurial > repos > blastem

comparison m68k_core_x86.c @ 1370:eaca4443e831

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Fix interrupt latency for move.l with memory destination
author Michael Pavone <pavone@retrodev.com>
date Tue, 23 May 2017 21:07:56 -0700
parents df6af7187b36
children b68732dcbf00
comparison
equal deleted inserted replaced
1369:3e7a921718de 1370:eaca4443e831
558 int8_t reg, flags_reg, sec_reg; 558 int8_t reg, flags_reg, sec_reg;
559 uint8_t dir = 0; 559 uint8_t dir = 0;
560 int32_t offset; 560 int32_t offset;
561 int32_t inc_amount, dec_amount; 561 int32_t inc_amount, dec_amount;
562 host_ea src; 562 host_ea src;
563 if (translate_m68k_op(inst, &src, opts, 0)) { 563 uint8_t needs_int_latch = translate_m68k_op(inst, &src, opts, 0);
564 m68k_check_cycles_int_latch(opts);
565 }
566 reg = native_reg(&(inst->dst), opts); 564 reg = native_reg(&(inst->dst), opts);
567 565
568 if (inst->dst.addr_mode != MODE_AREG) { 566 if (inst->dst.addr_mode != MODE_AREG) {
569 if (src.mode == MODE_REG_DIRECT) { 567 if (src.mode == MODE_REG_DIRECT) {
570 flags_reg = src.base; 568 flags_reg = src.base;
712 if (inst->dst.addr_mode != MODE_AREG) { 710 if (inst->dst.addr_mode != MODE_AREG) {
713 cmp_ir(code, 0, flags_reg, inst->extra.size); 711 cmp_ir(code, 0, flags_reg, inst->extra.size);
714 update_flags(opts, N|Z|V0|C0); 712 update_flags(opts, N|Z|V0|C0);
715 } 713 }
716 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) { 714 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) {
715 if (inst->extra.size == OPSIZE_LONG) {
716 //We want the int latch to occur between the two writes,
717 //but that's a pain to do without refactoring how 32-bit writes work
718 //workaround it by temporarily increasing the cycle count before the check
719 cycles(&opts->gen, BUS);
720 }
721 m68k_check_cycles_int_latch(opts);
722 if (inst->extra.size == OPSIZE_LONG) {
723 //and then backing out that extra increment here before the write happens
724 cycles(&opts->gen, -BUS);
725 }
717 m68k_write_size(opts, inst->extra.size, inst->dst.addr_mode == MODE_AREG_PREDEC); 726 m68k_write_size(opts, inst->extra.size, inst->dst.addr_mode == MODE_AREG_PREDEC);
718 if (inst->dst.addr_mode == MODE_AREG_POSTINC) { 727 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
719 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1)); 728 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1));
720 addi_areg(opts, inc_amount, inst->dst.params.regs.pri); 729 addi_areg(opts, inc_amount, inst->dst.params.regs.pri);
721 } 730 }
731 } else {
732 m68k_check_cycles_int_latch(opts);
722 } 733 }
723 734
724 //add cycles for prefetch 735 //add cycles for prefetch
725 cycles(&opts->gen, BUS); 736 cycles(&opts->gen, BUS);
726 } 737 }