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comparison m68k_to_x86.c @ 162:eba78ad49a11

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Implement more movem modes src
author Mike Pavone <pavone@retrodev.com>
date Sat, 05 Jan 2013 02:18:31 -0800
parents 6748022656b7
children 62b152811bae
comparison
equal deleted inserted replaced
161:6748022656b7 162:eba78ad49a11
1148 case MODE_AREG_POSTINC: 1148 case MODE_AREG_POSTINC:
1149 if (opts->aregs[inst->src.params.regs.pri] >= 0) { 1149 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
1150 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); 1150 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
1151 } else { 1151 } else {
1152 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); 1152 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
1153 }
1154 break;
1155 case MODE_AREG_DISPLACE:
1156 early_cycles += BUS;
1157 reg = SCRATCH2;
1158 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
1159 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
1160 } else {
1161 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
1162 }
1163 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
1164 break;
1165 case MODE_AREG_INDEX_DISP8:
1166 early_cycles += 6;
1167 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
1168 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
1169 } else {
1170 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
1171 }
1172 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
1173 if (inst->dst.params.regs.sec & 1) {
1174 if (inst->dst.params.regs.sec & 0x10) {
1175 if (opts->aregs[sec_reg] >= 0) {
1176 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
1177 } else {
1178 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
1179 }
1180 } else {
1181 if (opts->dregs[sec_reg] >= 0) {
1182 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
1183 } else {
1184 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
1185 }
1186 }
1187 } else {
1188 if (inst->dst.params.regs.sec & 0x10) {
1189 if (opts->aregs[sec_reg] >= 0) {
1190 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
1191 } else {
1192 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
1193 }
1194 } else {
1195 if (opts->dregs[sec_reg] >= 0) {
1196 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
1197 } else {
1198 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
1199 }
1200 }
1201 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
1202 }
1203 if (inst->dst.params.regs.displacement) {
1204 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
1205 }
1206 break;
1207 case MODE_PC_DISPLACE:
1208 early_cycles += BUS;
1209 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
1210 break;
1211 case MODE_PC_INDEX_DISP8:
1212 early_cycles += 6;
1213 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
1214 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
1215 if (inst->dst.params.regs.sec & 1) {
1216 if (inst->dst.params.regs.sec & 0x10) {
1217 if (opts->aregs[sec_reg] >= 0) {
1218 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
1219 } else {
1220 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
1221 }
1222 } else {
1223 if (opts->dregs[sec_reg] >= 0) {
1224 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
1225 } else {
1226 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
1227 }
1228 }
1229 } else {
1230 if (inst->dst.params.regs.sec & 0x10) {
1231 if (opts->aregs[sec_reg] >= 0) {
1232 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
1233 } else {
1234 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
1235 }
1236 } else {
1237 if (opts->dregs[sec_reg] >= 0) {
1238 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
1239 } else {
1240 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
1241 }
1242 }
1243 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
1244 }
1245 if (inst->dst.params.regs.displacement) {
1246 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
1153 } 1247 }
1154 break; 1248 break;
1155 case MODE_ABSOLUTE: 1249 case MODE_ABSOLUTE:
1156 early_cycles += 4; 1250 early_cycles += 4;
1157 case MODE_ABSOLUTE_SHORT: 1251 case MODE_ABSOLUTE_SHORT: