Mercurial > repos > blastem
comparison backend_x86.c @ 1086:f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
author | Michael Pavone <pavone@retrodev.com> |
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date | Thu, 06 Oct 2016 22:25:12 -0700 |
parents | 193db42e702b |
children | fc125af5e4f1 |
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1085:bc86eaf6699d | 1086:f0a1e0a2263c |
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79 and_ir(code, opts->address_mask, adr_reg, SZ_D); | 79 and_ir(code, opts->address_mask, adr_reg, SZ_D); |
80 } | 80 } |
81 code_ptr lb_jcc = NULL, ub_jcc = NULL; | 81 code_ptr lb_jcc = NULL, ub_jcc = NULL; |
82 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ; | 82 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ; |
83 uint32_t ram_flags_off = opts->ram_flags_off; | 83 uint32_t ram_flags_off = opts->ram_flags_off; |
84 uint32_t min_address = 0; | |
85 uint32_t max_address = opts->max_address; | |
84 for (uint32_t chunk = 0; chunk < num_chunks; chunk++) | 86 for (uint32_t chunk = 0; chunk < num_chunks; chunk++) |
85 { | 87 { |
86 if (memmap[chunk].start > 0) { | 88 if (memmap[chunk].start > min_address) { |
87 cmp_ir(code, memmap[chunk].start, adr_reg, opts->address_size); | 89 cmp_ir(code, memmap[chunk].start, adr_reg, opts->address_size); |
88 lb_jcc = code->cur + 1; | 90 lb_jcc = code->cur + 1; |
89 jcc(code, CC_C, code->cur + 2); | 91 jcc(code, CC_C, code->cur + 2); |
90 } | 92 } else { |
91 if (memmap[chunk].end < opts->max_address) { | 93 min_address = memmap[chunk].end; |
94 } | |
95 if (memmap[chunk].end < max_address) { | |
92 cmp_ir(code, memmap[chunk].end, adr_reg, opts->address_size); | 96 cmp_ir(code, memmap[chunk].end, adr_reg, opts->address_size); |
93 ub_jcc = code->cur + 1; | 97 ub_jcc = code->cur + 1; |
94 jcc(code, CC_NC, code->cur + 2); | 98 jcc(code, CC_NC, code->cur + 2); |
99 } else { | |
100 max_address = memmap[chunk].start; | |
95 } | 101 } |
96 | 102 |
97 if (memmap[chunk].mask != opts->address_mask) { | 103 if (memmap[chunk].mask != opts->address_mask) { |
98 and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size); | 104 and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size); |
99 } | 105 } |
228 or_ir(code, memmap[chunk].start, opts->scratch1, opts->address_size); | 234 or_ir(code, memmap[chunk].start, opts->scratch1, opts->address_size); |
229 } | 235 } |
230 call(code, opts->save_context); | 236 call(code, opts->save_context); |
231 call_args(code, opts->handle_code_write, 2, opts->scratch2, opts->context_reg); | 237 call_args(code, opts->handle_code_write, 2, opts->scratch2, opts->context_reg); |
232 mov_rr(code, RAX, opts->context_reg, SZ_PTR); | 238 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
233 call(code, opts->load_context); | 239 jmp(code, opts->load_context); |
234 *not_code = code->cur - (not_code+1); | 240 *not_code = code->cur - (not_code+1); |
235 } | 241 } |
236 retn(code); | 242 retn(code); |
237 } else if (cfun) { | 243 } else if (cfun) { |
238 call(code, opts->save_context); | 244 call(code, opts->save_context); |