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Byteswap ROMs in jaguar ROM loader. Handle switching memory map from writes to memcon1. Fix some typos in error messages
author Michael Pavone <pavone@retrodev.com>
date Thu, 06 Oct 2016 09:35:35 -0700
parents 382614130914
children bc86eaf6699d
comparison
equal deleted inserted replaced
1082:2ec5e6eaf81d 1083:f6e998227300
3 #include <stddef.h> 3 #include <stddef.h>
4 #include <stdlib.h> 4 #include <stdlib.h>
5 #include "m68k_core.h" 5 #include "m68k_core.h"
6 #include "jaguar.h" 6 #include "jaguar.h"
7 #include "util.h" 7 #include "util.h"
8 #include "debug.h"
8 9
9 //BIOS Area Memory map 10 //BIOS Area Memory map
10 // 10 00 00 - 10 04 00 : Video mode/ Memory control registers 11 // 10 00 00 - 10 04 00 : Video mode/ Memory control registers
11 // 10 04 00 - 10 08 00 : CLUT 12 // 10 04 00 - 10 08 00 : CLUT
12 // 10 08 00 - 10 10 00 : Line buffer A 13 // 10 08 00 - 10 10 00 : Line buffer A
34 } 35 }
35 if (address < 0x103000) { 36 if (address < 0x103000) {
36 if (address < 0x101000) { 37 if (address < 0x101000) {
37 if (address < 0x100400) { 38 if (address < 0x100400) {
38 //Video mode / Memory control registers 39 //Video mode / Memory control registers
39 fprintf(stderr, "Unhanelde write to video mode/memory control registers - %X:%X", address, value); 40 switch(address & 0x3FE)
41 {
42 case 0:
43 if (((value ^ system->memcon1) & 1) || !system->memcon_written) {
44 uint16_t **mem_pointers = system->m68k->mem_pointers;
45 int rom = value & 1 ? 4 : 1;
46 int ram0 = value & 1 ? 0 : 6;
47 int ram1 = value & 1 ? 2 : 4;
48 mem_pointers[ram0] = mem_pointers[ram0 + 1] = system->dram;
49 //these are probably open bus, but mirror DRAM for now
50 mem_pointers[ram1] = mem_pointers[ram1 + 1] = system->dram;
51
52 mem_pointers[rom] = system->cart;
53 mem_pointers[rom + 1] = system->cart + ((0x200000 & (system->cart_size-1)) >> 1);
54 mem_pointers[rom + 2] = system->cart + ((0x400000 & (system->cart_size-1)) >> 1);
55 system->memcon_written = 1;
56 //TODO: invalidate code cache
57 }
58 system->memcon1 = value;
59 break;
60 case 2:
61 system->memcon2 = value;
62 break;
63 default:
64 fprintf(stderr, "Unhandled write to video mode/memory control registers - %X:%X\n", address, value);
65 break;
66 }
40 } else if (address < 0x100800) { 67 } else if (address < 0x100800) {
41 //CLUT 68 //CLUT
42 address = address >> 1 & 255; 69 address = address >> 1 & 255;
43 system->clut[address] = value; 70 system->clut[address] = value;
44 } else { 71 } else {
76 value32 = value32 << 16; 103 value32 = value32 << 16;
77 } 104 }
78 system->gpu_local[offset] |= value32; 105 system->gpu_local[offset] |= value32;
79 } else if (address < 0x114000) { 106 } else if (address < 0x114000) {
80 //timer clock registers 107 //timer clock registers
81 fprintf(stderr, "Unhanelde write to timer/clock registers - %X:%X", address, value); 108 fprintf(stderr, "Unhandled write to timer/clock registers - %X:%X\n", address, value);
82 } else { 109 } else {
83 //joystick interface 110 //joystick interface
84 fprintf(stderr, "Unhanelde write to joystick interface - %X:%X", address, value); 111 fprintf(stderr, "Unhandled write to joystick interface - %X:%X\n", address, value);
85 } 112 }
86 } else if (address < 0x11B000) { 113 } else if (address < 0x11B000) {
87 //DSP/DAC/I2S Registers 114 //DSP/DAC/I2S Registers
88 fprintf(stderr, "Unhanelde write to DSP/DAC/I2S registers - %X:%X", address, value); 115 fprintf(stderr, "Unhandled write to DSP/DAC/I2S registers - %X:%X\n", address, value);
89 } else if (address < 0x11D000) { 116 } else if (address < 0x11D000) {
90 //DSP local RAM 117 //DSP local RAM
91 uint32_t offset = address >> 2 & (DSP_RAM_BYTES / sizeof(uint32_t) - 1); 118 uint32_t offset = address >> 2 & (DSP_RAM_BYTES / sizeof(uint32_t) - 1);
92 uint32_t value32 = value; 119 uint32_t value32 = value;
93 if (address & 2) { 120 if (address & 2) {
112 } 139 }
113 if (address < 0x103000) { 140 if (address < 0x103000) {
114 if (address < 0x101000) { 141 if (address < 0x101000) {
115 if (address < 0x100400) { 142 if (address < 0x100400) {
116 //Video mode / Memory control registers 143 //Video mode / Memory control registers
117 fprintf(stderr, "Unhandled read from video mode/memory control registers - %X", address); 144 fprintf(stderr, "Unhandled read from video mode/memory control registers - %X\n", address);
118 } else if (address < 0x100800) { 145 } else if (address < 0x100800) {
119 //CLUT 146 //CLUT
120 address = address >> 1 & 255; 147 address = address >> 1 & 255;
121 return system->clut[address]; 148 return system->clut[address];
122 } else { 149 } else {
151 } else { 178 } else {
152 return system->gpu_local[offset] >> 16; 179 return system->gpu_local[offset] >> 16;
153 } 180 }
154 } else if (address < 0x114000) { 181 } else if (address < 0x114000) {
155 //timer clock registers 182 //timer clock registers
156 fprintf(stderr, "Unhandled read from timer/clock registers - %X", address); 183 fprintf(stderr, "Unhandled read from timer/clock registers - %X\n", address);
157 } else { 184 } else {
158 //joystick interface 185 //joystick interface
159 fprintf(stderr, "Unhandled read from joystick interface - %X", address); 186 fprintf(stderr, "Unhandled read from joystick interface - %X\n", address);
160 } 187 }
161 } else if (address < 0x11B000) { 188 } else if (address < 0x11B000) {
162 //DSP/DAC/I2S Registers 189 //DSP/DAC/I2S Registers
163 fprintf(stderr, "Unhandled read from DSP/DAC/I2S registers - %X", address); 190 fprintf(stderr, "Unhandled read from DSP/DAC/I2S registers - %X\n", address);
164 } else if (address < 0x11D000) { 191 } else if (address < 0x11D000) {
165 //DSP local RAM 192 //DSP local RAM
166 uint32_t offset = address >> 2 & (DSP_RAM_BYTES / sizeof(uint32_t) - 1); 193 uint32_t offset = address >> 2 & (DSP_RAM_BYTES / sizeof(uint32_t) - 1);
167 if (address & 2) { 194 if (address & 2) {
168 return system->dsp_local[offset]; 195 return system->dsp_local[offset];
212 context->current_cycle -= 0x10000000; 239 context->current_cycle -= 0x10000000;
213 } 240 }
214 return context; 241 return context;
215 } 242 }
216 243
244 m68k_context *handle_m68k_reset(m68k_context *context)
245 {
246 puts("M68K executed RESET");
247 return context;
248 }
249
217 jaguar_context *init_jaguar(uint16_t *bios, uint32_t bios_size, uint16_t *cart, uint32_t cart_size) 250 jaguar_context *init_jaguar(uint16_t *bios, uint32_t bios_size, uint16_t *cart, uint32_t cart_size)
218 { 251 {
219 jaguar_context *system = calloc(1, sizeof(jaguar_context)); 252 jaguar_context *system = calloc(1, sizeof(jaguar_context));
220 system->bios = bios; 253 system->bios = bios;
221 system->bios_size = bios_size; 254 system->bios_size = bios_size;
222 system->cart = cart; 255 system->cart = cart;
223 system->cart_size = cart_size; 256 system->cart_size = cart_size;
224 257
225 memmap_chunk jag_m68k_map[8]; 258 memmap_chunk *jag_m68k_map = calloc(8, sizeof(memmap_chunk));
226 for (uint32_t start = 0, index=0; index < 8; index++, start += 0x200000) 259 for (uint32_t start = 0, index=0; index < 8; index++, start += 0x200000)
227 { 260 {
228 jag_m68k_map[index].start = start; 261 jag_m68k_map[index].start = start;
229 jag_m68k_map[index].end = start + 0x200000; 262 jag_m68k_map[index].end = start + 0x200000;
230 jag_m68k_map[index].mask = index ? 0x1FFFFF : 0xFFFFFF; 263 jag_m68k_map[index].mask = index ? 0x1FFFFF : 0xFFFFFF;
231 jag_m68k_map[index].aux_mask = bios_size - 1; 264 jag_m68k_map[index].aux_mask = bios_size - 1;
232 jag_m68k_map[index].ptr_index = index; 265 jag_m68k_map[index].ptr_index = index;
233 jag_m68k_map[index].flags = MMAP_READ | MMAP_WRITE | MMAP_PTR_IDX | MMAP_FUNC_NULL | MMAP_AUX_BUFF; 266 jag_m68k_map[index].flags = MMAP_READ | MMAP_WRITE | MMAP_PTR_IDX | MMAP_FUNC_NULL | MMAP_AUX_BUFF | MMAP_CODE;
234 jag_m68k_map[index].buffer = bios; 267 jag_m68k_map[index].buffer = bios;
235 jag_m68k_map[index].read_16 = rom0_read_m68k; 268 jag_m68k_map[index].read_16 = rom0_read_m68k;
236 jag_m68k_map[index].read_8 = rom0_read_m68k_b; 269 jag_m68k_map[index].read_8 = rom0_read_m68k_b;
237 jag_m68k_map[index].write_16 = rom0_write_m68k; 270 jag_m68k_map[index].write_16 = rom0_write_m68k;
238 jag_m68k_map[index].write_8 = rom0_write_m68k_b; 271 jag_m68k_map[index].write_8 = rom0_write_m68k_b;
239 } 272 }
240 m68k_options *opts = malloc(sizeof(m68k_options)); 273 m68k_options *opts = malloc(sizeof(m68k_options));
241 init_m68k_opts(opts, jag_m68k_map, 8, 2); 274 init_m68k_opts(opts, jag_m68k_map, 8, 2);
242 system->m68k = init_68k_context(opts); 275 system->m68k = init_68k_context(opts, handle_m68k_reset);
243 system->m68k->system = system; 276 system->m68k->system = system;
244 return system; 277 return system;
245 } 278 }
246 279
247 //modified copy of the version in blastem.c 280 //modified copy of the version in blastem.c
258 *size = nearest_pow2(filesize); 291 *size = nearest_pow2(filesize);
259 uint16_t *cart = malloc(*size); 292 uint16_t *cart = malloc(*size);
260 if (filesize != fread(cart, 1, filesize, f)) { 293 if (filesize != fread(cart, 1, filesize, f)) {
261 fatal_error("Error reading from %s\n", filename); 294 fatal_error("Error reading from %s\n", filename);
262 } 295 }
296 filesize = (filesize + 1) & ~1L;
297 for (long i = 0; i < filesize; i+=2)
298 {
299 long index = i >> 1;
300 cart[index] = cart[index] >> 8 | cart[index] << 8;
301 }
263 while (filesize < *size) 302 while (filesize < *size)
264 { 303 {
265 cart[filesize / 2] = 0xFFFF; 304 cart[filesize / 2] = 0xFFFF;
266 filesize += 2; 305 filesize += 2;
267 } 306 }